参数资料
型号: IP-FIR
厂商: Altera
文件页数: 20/76页
文件大小: 0K
描述: IP FIR COMPILER
标准包装: 1
系列: *
类型: MegaCore
功能: 有限脉冲响应编译器
许可证: 初始许可证
2–6
Chapter 2: Getting Started
MegaWizard Plug-In Manager Flow
Generate the MegaCore Function
To generate your MegaCore function variation, perform the following steps:
1. Click Step 3: Generate in IP Toolbench to generate your MegaCore function
variation and supporting files. The generation phase may take several minutes to
complete. The generation progress and status is displayed in a report window.
Figure 2–6 shows the generation report.
Figure 2–6. Generation Report - FIR Compiler MegaCore Function
Table 2–1 describes the IP Toolbench-generated files and other files that may be in
your project directory. The names and types of files specified in the report vary
based on whether you created your design with VHDL or Verilog HDL.
Table 2–1. Generated Files (Part 1 of 2) (Note 1) , (2)
Filename
< entity name >.vhd
< variation name >.bsf
< variation name >.cmp
< variation name >.html
< variation name >.qip
Description
A VHDL wrapper file for the Avalon-ST interface.
A Quartus II block symbol file for the MegaCore function variation. You can use this
file in the Quartus II block diagram editor.
A VHDL component declaration file for the MegaCore function variation. Add the
contents of this file to any VHDL architecture that instantiates the MegaCore function.
A MegaCore function report file in hypertext markup language format.
A single Quartus II IP file is generated that contains all of the assignments and other
information required to process your MegaCore function variation in the Quartus II
compiler. You are prompted to add this file to the current Quartus II project when you
exit from IP Toolbench.
? May 2011 Altera Corporation
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