参数资料
| 型号： | IP-FIR |
| 厂商： | Altera |
| 文件页数： | 64/76页 |
| 文件大小： | 0K |
| 描述： | IP FIR COMPILER |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | 有限脉冲响应编译器 |
| 许可证： | 初始许可证 |
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4–22
Chapter 4: Functional Description
Timing Diagrams
Figure 4–22. Single Channel, Decimation-by-2 (Parallel, MCV Single Cycle)
If the filter is time-shared by N , (that is the Clocks to compute value is N ), then new
input data is required every N clock cycles and new output data is produced every
N × M cycles.
and an input data width of 8-bits.
Figure 4–23. Three Channel, Decimation Filter (Serial, MBS, MCV Multicycle)
The filter needs new data every four clock cycles and produces an output every 8
clock cycles. Because the flow is controlled by ast_sink_ready , the input data
fetching occurs in a groups, where ast_sink_ready goes high for five cycles and
five new data inputs are taken at once. Then ast_sink_ready goes low and no data
is accepted for 15 cycles. The ast_source_sop and ast_source_eop signals mark
the start of packet and end of packet respectively.
Coefficient Reloading Timing Diagrams
The coefficient reload ports are not Avalon-ST compliant and work independently of
the enable and reset signals, and of the Avalon-ST controller. You can load new
coefficients even if the filter is under reset conditions or not enabled.
Serial, multibit serial, and parallel FIR filters use a distributed arithmetic algorithm
and the coefficients stored in memory blocks are precalculated. When updating the
coefficients, the new coefficients first go through a pre-calculating algorithm. The first
data to reload in each memory block is always zero. The rising edge of the coef_we
signal resets the internal data address counter for reloading.
? May 2011 Altera Corporation
相关PDF资料 |
PDF描述 |
|---|---|
| IP-NCO | IP NCO COMPILER |
| IP-NIOS | IP NIOS II MEGACORE |
| IP-PCI/MT64 | IP PCI 64BIT MASTER/TARGET |
| IP-PCIE/8 | IP PCI EXPRESS, X8 |
| IP-POSPHY4 | IP POS-PHY L4 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IP-FIRII | 功能描述:开发软件 FIR Compiler II MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPFLBPT2 | 制造商:Carlo Gavazzi 功能描述:IL 35MM MUSH P-P PL 22MM RED |
| IPG1-0-90 | 制造商:Sensata Technologies 功能描述:1 Pole |
| IPG1-1-41-203-90 | 制造商:Sensata Technologies 功能描述:1 Pole |
| IPG1-1-51-103-A-00-V | 制造商:Sensata Technologies 功能描述:Circuit Breaker Magnetic 1Pole 10A 65VDC |
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