参数资料
| 型号： | IP-FIR |
| 厂商： | Altera |
| 文件页数： | 66/76页 |
| 文件大小： | 0K |
| 描述： | IP FIR COMPILER |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | 有限脉冲响应编译器 |
| 许可证： | 初始许可证 |
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4–24
1
Chapter 4: Functional Description
Timing Diagrams
Multicycle variable reloading is faster than the fixed FIR (with reloading capability).
Coefficients need sequence adjustment using the same algorithm as fixed FIR filters
for all types of coefficient storage. The reloading clock is the same as the FIR filter
calculation clock; coef_we should be triggered by the coef_ld signal.
When the coefficients are stored in logic cells, a reloaded coefficient set reverts backs
to the original set after a reset operation.
the coefficients are stored in logic cells.
Figure 4–26. Multicycle Variable (Using Logic Cells) Coefficient Reloading Timing Diagram
Coef_we is valid one clock cycle after effective coef_ld
clk
reset_n
coef_ld
coef_we
coef_in
0
-114
-12
-10
0
-16
-127
-16
ast_sink_ready
ast_sink_data
ast_source_valid
ast_source_data
0
0
Input coefficients coef_in are sequence adjusted
For multicycle variable FIR filters, when coefficients are stored in memory blocks,
coef_we should be effective two clock cycles before the first coef_in data, and
should last until the last coef_in data is transmitted. Coefficients can be
transmitted from c0 to cn by a different clock.
the coefficients are stored in memory blocks.
Figure 4–27. Multicycle Variable (Using Memory Blocks) Coefficient Reloading Timing Diagram
coef_we is effective two clock cycles before first coef_in data
clk
ast_sink_ready
ast_sink_data
coef_in_clk
coef_we
0
coef_in
5
-114
-12
-10
0
-16
-127
-16
8
ast_source_valid
ast_source_data
0
Coefficients from c0 to cN
If you use multiple coefficient sets, you can update one set of coefficients while using
another set for calculation. The signals coef_set_in and coef_we are not clocked
in and pipelined synchronously. While you update the coefficient set, you need to set
and hold the coef_set_in signal for several cycles before coef_we is asserted and
after it is de-asserted.
? May 2011 Altera Corporation
相关PDF资料 |
PDF描述 |
|---|---|
| IP-NCO | IP NCO COMPILER |
| IP-NIOS | IP NIOS II MEGACORE |
| IP-PCI/MT64 | IP PCI 64BIT MASTER/TARGET |
| IP-PCIE/8 | IP PCI EXPRESS, X8 |
| IP-POSPHY4 | IP POS-PHY L4 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IP-FIRII | 功能描述:开发软件 FIR Compiler II MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPFLBPT2 | 制造商:Carlo Gavazzi 功能描述:IL 35MM MUSH P-P PL 22MM RED |
| IPG1-0-90 | 制造商:Sensata Technologies 功能描述:1 Pole |
| IPG1-1-41-203-90 | 制造商:Sensata Technologies 功能描述:1 Pole |
| IPG1-1-51-103-A-00-V | 制造商:Sensata Technologies 功能描述:Circuit Breaker Magnetic 1Pole 10A 65VDC |
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