参数资料
| 型号： | IP-FIR |
| 厂商： | Altera |
| 文件页数： | 57/76页 |
| 文件大小： | 0K |
| 描述： | IP FIR COMPILER |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | 有限脉冲响应编译器 |
| 许可证： | 初始许可证 |
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Chapter 4: Functional Description
4–15
Avalon Streaming Interface
The sink indicates to the source that it is ready for an active cycle by asserting the
ready signal for a single clock cycle. Cycles during which the sink is ready for data
are called ready cycles . During a ready cycle, the source may assert valid and provide
data to the sink. If it has no data to send, it deasserts valid and can drive data to any
value.
When READY_LATENCY=0, data is transferred only when ready and valid are
asserted on the same cycle. In this mode of operation, the source data does not need to
receive the sink’s ready signal before it begins sending valid data. The source
provides the data and asserts valid whenever it can and waits for the sink to capture
the data and assert ready . The sink only captures input data from the source when
ready and valid are both asserted.
Figure 4–12. Avalon-ST Interface Timing with READY_LATENCY=0
0
1
2
3
4
5
6
7
8
clk
ready
valid
error
data
00
D o
00
D 1
00
D 2
00
D 2
The source provides data and asserts valid on cycle 1, even though the sink is not
ready. The source waits until cycle 2, when the sink does assert ready , before moving
onto the next data cycle. In cycle 3, the source drives data on the same cycle and
because the sink is ready to receive it, the transfer occurs immediately. In cycle 4, the
sink asserts ready , but the source does not drive valid data.
Packet Data Transfers
A beat is defined as the transfer of one unit of data between a source and sink
interface. This unit of data may consist of one or more symbols and makes it is
possible to support modules that convey more than one piece of information about
each valid cycle. Packet data transfers are used for multichannel transfers. Two
additional signals ( startofpacket and endofpacket ) are defined to implement
the packet transfer.
data sample belongs.
Figure 4–13. Packet Data Transfer
1
2
3
4
5
6
7
clk
ready
valid
startofpacket
endofpacket
channel[1:0]
error[1:0]
data
0
00
D 0
1
00
D 1
2
00
D 2
3
00
D 3
1
The channel input signal is not used in the FIR Compiler interface.
? May 2011
Altera Corporation
相关PDF资料 |
PDF描述 |
|---|---|
| IP-NCO | IP NCO COMPILER |
| IP-NIOS | IP NIOS II MEGACORE |
| IP-PCI/MT64 | IP PCI 64BIT MASTER/TARGET |
| IP-PCIE/8 | IP PCI EXPRESS, X8 |
| IP-POSPHY4 | IP POS-PHY L4 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IP-FIRII | 功能描述:开发软件 FIR Compiler II MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPFLBPT2 | 制造商:Carlo Gavazzi 功能描述:IL 35MM MUSH P-P PL 22MM RED |
| IPG1-0-90 | 制造商:Sensata Technologies 功能描述:1 Pole |
| IPG1-1-41-203-90 | 制造商:Sensata Technologies 功能描述:1 Pole |
| IPG1-1-51-103-A-00-V | 制造商:Sensata Technologies 功能描述:Circuit Breaker Magnetic 1Pole 10A 65VDC |
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