参数资料
型号: IP-FIR
厂商: Altera
文件页数: 62/76页
文件大小: 0K
描述: IP FIR COMPILER
标准包装: 1
系列: *
类型: MegaCore
功能: 有限脉冲响应编译器
许可证: 初始许可证
4–20
Chapter 4: Functional Description
Timing Diagrams
Figure 4–17. Single Channel, Single Rate (Serial, Multibit Serial, MCV Multicycle), ast_sink_valid Control
Figure 4–18. Single Channel, Single Rate (Serial, Multibit Serial, MCV Multicycle) ast_sink_ready Control
In Figure 4–17 , the flow is controlled by the data provider asserting
ast_sink_valid every three clock cycles.
In Figure 4–18 , ast_sink_valid is always held high and the data provider can feed
new data in every clock cycle, but the filter accepts new data every three clock cycles
by asserting ast_sink_ready .
In this scenario, a number of data samples are fetched at once and then
ast_sink_ready is de-asserted for a longer period. This behavior is due to the
internal buffering of the Avalon-ST controller.
Interpolation Filter Timing Diagrams
Figure 4–19 and Figure 4–20 on page 4–21 show a single channel interpolation-by-2
filter with a parallel architecture.
Figure 4–19. Single Channel, Interpolation-by-2 (Parallel, MCV Single Cycle), ast_sink_valid Control
? May 2011 Altera Corporation
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