参数资料
| 型号： | IP-FIR |
| 厂商： | Altera |
| 文件页数： | 54/76页 |
| 文件大小： | 0K |
| 描述： | IP FIR COMPILER |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | 有限脉冲响应编译器 |
| 许可证： | 初始许可证 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页当前第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页
4–12
1
Chapter 4: Functional Description
FIR Compiler
All multicycle variable structures allow the use of hard multipliers in Stratix IV,
Stratix III, Stratix II, Stratix, Cyclone III, and Cyclone II structures. In addition,
Stratix IV, Stratix III, Stratix II, and Stratix multicycle variable implementations take
advantage of the built-in adder structures in the DSP block.
Stratix series devices allow the most flexibility for data and coefficient storage. You
can choose between M512, M4K, and MRAM (when appropriate) for Stratix and
Stratix II devices. Stratix III and Stratix IV devices support MLAB, M9K, and M144K.
Half-Band Decimation Filters
A decimation half-band optimized architecture is available for multicycle variable
structures. This architecture uses half the number of multipliers compared to the
decimation-symmetric architecture when a half-band coefficient set is selected. A
halfband coefficient set has an odd number of symmetric coefficients and every other
coefficient value is 0.
Currently only a single fixed-coefficient set is supported with this optimized
architecture. The data storage and coefficient storage should be set to either Auto or
one of the available block memories. Any value for the decimation factor and the
number of channels can be selected. The number of clocks to compute should be
greater than 1. The FIR Compiler automatically picks the decimation half-band
optimized architecture when these conditions are met.
Symmetric-Interpolation Filters
A new symmetric-interpolation optimized architecture is available for multicycle
variable structures. This architecture requires half the number of multipliers
compared to the standard interpolation filter when a symmetric coefficient set is
selected.
The number of filter taps should be an odd value. Currently only a single fixed-
coefficient set is supported with the optimized architecture. The data storage and
coefficient storage should be set to either Auto or one of the available block
memories. Any value for interpolation factor and number of channels can be selected.
The number of clocks to compute should be greater than 1. The FIR compiler
automatically picks the optimized architecture when these conditions are met.
Pipelining
Pipelining is most effective for producing high-performance filters at the cost of
increased latency: the more pipeline stages you add, the faster the filter becomes.
1
Pipelining breaks long carry chains into shorter lengths. Therefore, if the carry chains
in your design are already short, adding pipelining may not speed your design.
The FIR Compiler lets you select whether to add one, two, or three pipeline levels.
? May 2011 Altera Corporation
相关PDF资料 |
PDF描述 |
|---|---|
| IP-NCO | IP NCO COMPILER |
| IP-NIOS | IP NIOS II MEGACORE |
| IP-PCI/MT64 | IP PCI 64BIT MASTER/TARGET |
| IP-PCIE/8 | IP PCI EXPRESS, X8 |
| IP-POSPHY4 | IP POS-PHY L4 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IP-FIRII | 功能描述:开发软件 FIR Compiler II MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPFLBPT2 | 制造商:Carlo Gavazzi 功能描述:IL 35MM MUSH P-P PL 22MM RED |
| IPG1-0-90 | 制造商:Sensata Technologies 功能描述:1 Pole |
| IPG1-1-41-203-90 | 制造商:Sensata Technologies 功能描述:1 Pole |
| IPG1-1-51-103-A-00-V | 制造商:Sensata Technologies 功能描述:Circuit Breaker Magnetic 1Pole 10A 65VDC |
发布紧急采购，3分钟左右您将得到回复。