参数资料
| 型号： | IP-FIR |
| 厂商： | Altera |
| 文件页数： | 67/76页 |
| 文件大小： | 0K |
| 描述： | IP FIR COMPILER |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | 有限脉冲响应编译器 |
| 许可证： | 初始许可证 |
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Chapter 4: Functional Description
4–25
Timing Diagrams
The selection of the coefficient set for calculation is also not synchronous to the input
data because of the Avalon-ST flow controller. Once the coef_set signal is set to a
particular value, it immediately affects the operation of the filter. This means that
some of the input data already received by the Avalon-ST controller will be calculated
using the new coefficient set ( Figure 4–28 ).
Figure 4–28. Multiple Coefficient Set Selection Timing Diagram
clk
ast_sink_ready
Due to Avalon-ST buffering, this and some of the previous
data values can also be calculated with coef_set1.
This data is calculated
with coef_set1
ast_sink_data
0
113
-69
26
73
-56
coef_in_clk
coef_we
coef_in
coef_set
coef_set_in
ast_source_valid
0
ast_source_data
0
-791
82
1
For DSP Builder users, a button is available that ties the coef_in_clk to the clk in
the wrapper. DSP Builder will not work with more than one clock domain per
MegaCore function.
When loading multiple coefficient sets, to identify the coefficient set being loaded, the
duration of the clock cycle for coef_set_in must be one clock cycle longer than the
These timing requirements affect all designs that load multiple coefficient sets. If the
specified timing requirements are not met when loading multiple coefficient sets, a
specific set of coefficients will not be identified.
Figure 4–29. Timing Requirements for Loading Multiple Coefficient Sets
clk
ast_sink_ready
ast_sink_data
0
1
0
coef_we
coef_in
0
18
-2
-7
-1
0
0
coef_set
coef_set_in
ast_source_valid
ast_source_data
0
coef_set_in must be sustained one clock cycle longer than coef_we
18
? May 2011
Altera Corporation
相关PDF资料 |
PDF描述 |
|---|---|
| IP-NCO | IP NCO COMPILER |
| IP-NIOS | IP NIOS II MEGACORE |
| IP-PCI/MT64 | IP PCI 64BIT MASTER/TARGET |
| IP-PCIE/8 | IP PCI EXPRESS, X8 |
| IP-POSPHY4 | IP POS-PHY L4 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IP-FIRII | 功能描述:开发软件 FIR Compiler II MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPFLBPT2 | 制造商:Carlo Gavazzi 功能描述:IL 35MM MUSH P-P PL 22MM RED |
| IPG1-0-90 | 制造商:Sensata Technologies 功能描述:1 Pole |
| IPG1-1-41-203-90 | 制造商:Sensata Technologies 功能描述:1 Pole |
| IPG1-1-51-103-A-00-V | 制造商:Sensata Technologies 功能描述:Circuit Breaker Magnetic 1Pole 10A 65VDC |
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