参数资料
| 型号： | IP-FIR |
| 厂商： | Altera |
| 文件页数： | 58/76页 |
| 文件大小： | 0K |
| 描述： | IP FIR COMPILER |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | 有限脉冲响应编译器 |
| 许可证： | 初始许可证 |
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4–16
1
Chapter 4: Functional Description
Signals
The data transfer in Figure 4–13 occurs on cycles 1, 2, 4, and five, when both ready
and valid are asserted. During cycle 1, startofpacket is asserted, and the first
data is transferred. During cycle 5, endofpacket is asserted indicating that this is the
end of the packet.
The channel signal indicates the channel index associated with the data. For
example, on cycle 1, the data D 0 associated with channel 0 is available.
The error signal stays at value 00 during a normal operation. Whenever a value
other than 00 is received from the data source (as in Figure 4–11 ), or a packet error is
detected by the Avalon-ST controller of the FIR filter, the controller is reset and waits
for the next valid startofpacket signal. It also transmits the received error signal
from its data source module error output.
The error signal only resets the Avalon-ST controller and not the design. Therefore,
the output data produced after an error condition may contain invalid data for several
cycles. It is recommended that a global reset is applied whenever an error message is
present in the system.
Signals
Table 4–3. FIR Compiler Signals (Part 1 of 2)
Signal
clk
enable
reset_n
ast_sink_ready
ast_sink_valid
ast_sink_data
ast_sink_sop
ast_sink_eop
ast_sink_error
ast_source_ready
ast_source_valid
Direction
Input
Input
Input
Output
Input
Input
Input
Input
Input
Input
Output
Description
Clock signal used to clock all internal FIR filter registers.
Active high clock enable signal. This pin appears when the Add global clock
enable pin option is selected on the Parameterize FIR Compiler page. (The
Avalon-ST registers are NOT connected to this clock enable.)
Synchronous active low reset signal. Resets the FIR filter control circuit on the
rising edge of clk . This signal should last longer than one clock cycle.
Asserted by the FIR filter when it is able to accept data in the current clock cycle.
Asserted when input data is valid. When ast_sink_valid is not asserted, the
FIR processing is stopped if new data is required and no data is left in the Avalon-
ST input FIFO. Otherwise, the FIR processing continues.
Sample input data.
Marks the start of the incoming sample group. The start of packet (SOP) is
interpreted as a sample from channel 0.
Marks the end of the incoming sample group. If there is data associated with N
channels, the end of packet (EOP) must be high when the sample belonging to the
last channel (that is, channel N -1), is presented at the data input.
Error signal indicating Avalon-ST protocol violations on the sink side:
00: No error
■
01: Missing SOP
■
10: Missing EOP
■
11: Unexpected EOP
■
Other types of errors are also marked as 11.
Asserted by the downstream module if it is able to accept data.
Asserted by the FIR filter when there is valid data to output.
? May 2011 Altera Corporation
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