参数资料
| 型号： | IP-FIR |
| 厂商： | Altera |
| 文件页数： | 65/76页 |
| 文件大小： | 0K |
| 描述： | IP FIR COMPILER |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | 有限脉冲响应编译器 |
| 许可证： | 初始许可证 |
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Chapter 4: Functional Description
4–23
Timing Diagrams
For information about how to pre-calculate coefficients, refer to “Coefficient
In serial and multibit serial filters, coef_we is effective two clock cycles ahead of the
first coef_in data and lasts until the last coef_in data is transmitted. In parallel
filters, coef_we only needs to be effective one clock cycle ahead of the first coef_in
data. To reload another set of coefficients, coef_we must be low for at least one clock
cycle. The reload clock does not have to be the same clock as the one used by the FIR
calculation.
Figure 4–24. Serial and Multibit Serial Coefficient Reloading Timing Diagram
clk
reset_n
ast_sink_ready
Clock to reload coefficients
Precalculated coefficient values
ast_sink_data
0
1
-1
0
coef_in_clk
coef_we
coef_in
0
0
7
5
12
0
coef_set
coef_set_in
ast_source_valid
ast_source_data
0
coef_we should be two clock cycles ahead of coef_in (First data is always 0)
Figure 4–25. Parallel Coefficient Reloading Timing Diagram
clk
reset_n
ast_sink_data
coef_in_clk
coef_we
0
coef_in
0
0
7
5
12
0
7
coef_set
coef_set_in
coef_we should be one clock cycle ahead of coef_in (First data is always 0)
1
Serial, multibit serial, and parallel FIR architectures use a distributed arithmetic
algorithm. In the algorithm, look-up tables store partial products of the coefficient; the
first data of the partial product is always 0. When reloading pre-calculated coefficients
in serial, multibit serial, and parallel architectures, the first reloading coefficient is
always 0.
For information about how to pre-calculate coefficients, refer to “Coefficient
? May 2011
Altera Corporation
相关PDF资料 |
PDF描述 |
|---|---|
| IP-NCO | IP NCO COMPILER |
| IP-NIOS | IP NIOS II MEGACORE |
| IP-PCI/MT64 | IP PCI 64BIT MASTER/TARGET |
| IP-PCIE/8 | IP PCI EXPRESS, X8 |
| IP-POSPHY4 | IP POS-PHY L4 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IP-FIRII | 功能描述:开发软件 FIR Compiler II MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPFLBPT2 | 制造商:Carlo Gavazzi 功能描述:IL 35MM MUSH P-P PL 22MM RED |
| IPG1-0-90 | 制造商:Sensata Technologies 功能描述:1 Pole |
| IPG1-1-41-203-90 | 制造商:Sensata Technologies 功能描述:1 Pole |
| IPG1-1-51-103-A-00-V | 制造商:Sensata Technologies 功能描述:Circuit Breaker Magnetic 1Pole 10A 65VDC |
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