参数资料
| 型号： | IP-FIR |
| 厂商： | Altera |
| 文件页数： | 55/76页 |
| 文件大小： | 0K |
| 描述： | IP FIR COMPILER |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | 有限脉冲响应编译器 |
| 许可证： | 初始许可证 |
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Chapter 4: Functional Description
4–13
Simulation Output
Simulation Output
The FIR Compiler generates a number of output files for design simulation. After you
have created a custom FIR filter, you can use the output files with MATLAB or VHDL
simulation tools. You can use the test vectors and MATLAB software to simulate your
design.
1
IP functional simulation models will output correct data only when data storage is
clear. When data storage is not clear, functional simulation models will output non-
relevant data. The number of clock cycles it takes before relevant samples are
available is N; where N = (number of channels) × (number of coefficients) × (number
of clock cycles to calculate an output).
For a full list of files generated by the FIR Compiler, refer to Table 2–1 on page 2–6 .
Avalon Streaming Interface
The Avalon ? Streaming (Avalon-ST) interface defines a standard, flexible, and
modular protocol for data transfers from a source interface to a sink interface and
simplifies the process of controlling the flow of data in a datapath.
Avalon-ST interface signals can describe traditional streaming interfaces supporting a
single stream of data without knowledge of channels or packet boundaries.
Such interfaces typically contain data, ready, and valid signals. The Avalon-ST
interface can also support more complex protocols for burst and packet transfers with
packets interleaved across multiple channels.
The Avalon-ST interface inherently synchronizes multi-channel designs, which allows
you to achieve efficient, time-multiplexed implementations without having to
implement complex control logic.
The Avalon-ST interface supports backpressure, which is a flow control mechanism
where a sink can signal to a source to stop sending data. The sink typically uses
backpressure to stop the flow of data when its FIFO buffers are full or when there is
congestion on its output.
When designing a datapath which includes the FIR Compiler MegaCore function, you
may not need backpressure if you know the downstream components can always
receive data. You may achieve a higher clock rate by driving the ast_source_ready
signal of the FIR Compiler high, and not connecting the ast_sink_ready signal.
1
The coefficient reload related ports and coefficient set selection ports in multi-set
filters are not Avalon Streaming compliant.
The Avalon Interface Specifications define parameters which can be used to specify any
type of Avalon-ST interface. Table 4–1 on page 4–14 lists the values of these
parameters that are defined for the Avalon-ST interfaces used by the FIR Compiler.
All parameters not explicitly listed in the table have undefined values.
? May 2011
Altera Corporation
相关PDF资料 |
PDF描述 |
|---|---|
| IP-NCO | IP NCO COMPILER |
| IP-NIOS | IP NIOS II MEGACORE |
| IP-PCI/MT64 | IP PCI 64BIT MASTER/TARGET |
| IP-PCIE/8 | IP PCI EXPRESS, X8 |
| IP-POSPHY4 | IP POS-PHY L4 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IP-FIRII | 功能描述:开发软件 FIR Compiler II MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPFLBPT2 | 制造商:Carlo Gavazzi 功能描述:IL 35MM MUSH P-P PL 22MM RED |
| IPG1-0-90 | 制造商:Sensata Technologies 功能描述:1 Pole |
| IPG1-1-41-203-90 | 制造商:Sensata Technologies 功能描述:1 Pole |
| IPG1-1-51-103-A-00-V | 制造商:Sensata Technologies 功能描述:Circuit Breaker Magnetic 1Pole 10A 65VDC |
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