参数资料
| 型号： | IP-FIR |
| 厂商： | Altera |
| 文件页数： | 59/76页 |
| 文件大小： | 0K |
| 描述： | IP FIR COMPILER |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | 有限脉冲响应编译器 |
| 许可证： | 初始许可证 |
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Chapter 4: Functional Description
Timing Diagrams
Table 4–3. FIR Compiler Signals (Part 2 of 2)
4–17
ast_source_channel Output
Indicates the index of the channel whose result is presented at the data output.
The width of this signal = log 2 (number of channels).
ast_source_data
ast_source_sop
ast_source_eop
ast_source_error
coef_set
coef_in_clk
coef_set_in
coef_in
coef_we
coef_ld
Output
Output
Output
Output
Input
Input
Input
Input
Input
Output
Filter output. The data width depends on the parameter settings.
Marks the start of the outgoing FIR filter result group. If '1', a result
corresponding to channel 0 is output.
Marks the end of the outgoing FIR filter result group. If '1', a result corresponding
to channel N -1 is output, where N is the number of channels.
Error signal indicating Avalon-ST protocol violations on the source side:
00: No error
■
01: Missing SOP
■
10: Missing EOP
■
11: Unexpected EOP
■
Other types of errors are also marked as 11.
Selects which coefficient set the FIR filter uses for the calculation. (Appears when
multiple coefficient sets are used.) The width of this signal = log 2 (number of
coefficient sets).
Clock to reload coefficients when coefficients are stored in memory. (Appears
when the Coefficient Reload option is selected and the Use Single Clock option is
not selected) This clock can be different than clk .
Selects which coefficient set to be reloaded. (Appears when multiple coefficient
sets are used and the Coefficient Reload option is selected.) The width of this
signal = log 2 (number of coefficient sets)
Input coefficient value when reloading coefficient. (Appears when the Coefficient
Reload option is selected)
Active high write enable signal. Enables coefficient overwriting when coefficients
are reloadable.
Coefficient reload control port. This port is created only when multicycle filters are
selected and the coefficient storage is logic cells.
Timing Diagrams
The reset_n signal resets the control logic and state machines that control the FIR
Compiler (not including data storage elements that hold previous inputs used to
calculate the result).
The previous data is not cleared when the reset_n signal is applied. To clear the
data, set the ast_sink_data port to 0 for n clock cycles, where n = ( number of
coefficients ) × ( number of input channels ) × ( number of clock cycles needed to compute a FIR
result ).
The FIR output value depends on the coefficient values in the design. Therefore, the
timing diagrams of your own design may be different than those shown in the
following figures. However, you can use the testbench generated by the FIR compiler
to get the correct timing relation between signals for a specific parameterized case.
All timing diagrams assume a full streaming operation where ast_source_ready
and ast_sink_ready are always 1 (unless otherwise stated).
? May 2011
Altera Corporation
相关PDF资料 |
PDF描述 |
|---|---|
| IP-NCO | IP NCO COMPILER |
| IP-NIOS | IP NIOS II MEGACORE |
| IP-PCI/MT64 | IP PCI 64BIT MASTER/TARGET |
| IP-PCIE/8 | IP PCI EXPRESS, X8 |
| IP-POSPHY4 | IP POS-PHY L4 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IP-FIRII | 功能描述:开发软件 FIR Compiler II MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPFLBPT2 | 制造商:Carlo Gavazzi 功能描述:IL 35MM MUSH P-P PL 22MM RED |
| IPG1-0-90 | 制造商:Sensata Technologies 功能描述:1 Pole |
| IPG1-1-41-203-90 | 制造商:Sensata Technologies 功能描述:1 Pole |
| IPG1-1-51-103-A-00-V | 制造商:Sensata Technologies 功能描述:Circuit Breaker Magnetic 1Pole 10A 65VDC |
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