参数资料
| 型号： | IP-SRAM/QDRII |
| 厂商： | Altera |
| 文件页数： | 21/68页 |
| 文件大小： | 0K |
| 描述： | IP QDRII SRAM CONTROLLER |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | QDRII SRAM 控制器 |
| 许可证： | 初始许可证 |
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Getting Started
Simulate the
This section describes the following simulation techniques:
Example Design
■
Simulate with IP Functional Simulation Models
■
■
■
Simulating With the ModelSim Simulator
Simulating With Other Simulators
Simulating in Third-Party Simulation Tools Using NativeLink
Simulate with IP Functional Simulation Models
You can simulate the example design using the IP Toolbench-generated IP
functional simulation models. IP Toolbench generates a VHDL or Verilog
HDL testbench for your example design, which is in the testbench
directory in your project directory.
f
For more information on the testbench, refer to “Example Design” on
page 3–27 .
You can use the IP functional simulation model with any
Altera-supported VHDL or Verilog HDL simulator. The instructions for
the ModelSim simulator are different to other simulators.
Simulating With the ModelSim Simulator
Altera supplies a generic memory model, lib\qdrii_model.v , which
allows you to simulate the example design with the ModelSim simulator.
To simulate the example design with the ModelSim ? simulator, follow
these steps:
1.
2.
3.
4.
5.
Copy the generic memory model to the < directory name > testbench
directory.
Open the memory model and the testbench ( <top-level
name> _vsim.v or .vhd ) in a text editor and ensure the signal names
have the same capitalization in both files.
Start the ModelSim-Altera simulator.
Change your working directory to your IP Toolbench-generated file
directory < directory name > testbench\modelsim.
To simulate with an IP functional simulation model simulation, type
the following command:
source <variation name> _vsim.tcl r
Altera Corporation
MegaCore Version 9.1 2–11
November 2009
QDRII SRAM Controller MegaCore Function User Guide
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