参数资料
| 型号： | IP-SRAM/QDRII |
| 厂商： | Altera |
| 文件页数： | 41/68页 |
| 文件大小： | 0K |
| 描述： | IP QDRII SRAM CONTROLLER |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | QDRII SRAM 控制器 |
| 许可证： | 初始许可证 |
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Functional Description
Figure 3–5. Block Diagram of the New Read Capture Implementation
I/O
Fabric
cqn
A
Latch
EN
B
Routing
Delay
cq
Routing
Delay
To
FIFO
Buffer
Clock
Net w ork
Delay
The data from the latch becomes valid following the rising edge of the cq
signal (when the latch becomes transparent) and, in a worst-case
condition, becomes invalid following the rising edge of cqn signal (when
roughly half a cycle = t KHKH ), which is done by creating a zero-cycle path
between the latch and a device register. The data is re-captured in the
device using the same edge of the cq signal that makes the latch
transparent. Both the cq signal and the data cross the IOE-to-device
boundary where they are delayed. The cq signal is delayed by slightly
more than by the data needed to meet the setup time for this register.
However, the delay is not enough to violate its hold time,which is related
to the rising edge of cqn signal. Because the data is recaptured in the
FPGA while the latch is valid, the IOE capture register timing margins are
not impacted.
Figure 3–6 is a timing diagram of the IOE that assumes the latch is still
transparent when cqn rising edge occurs. The real B , expected B , and
delayed cq signals represent the data and clock to the re-capture
registers. The output of latch B is either real B or expected B , depending
on the relationship between cq and cqn . To cover both cases, the usable
part of B signal should be captured before going to the resynchronization
FIFO buffers. Routing delay aligns the data with the clock.
Altera Corporation
MegaCore Version 9.1 3–9
November 2009
QDRII SRAM Controller MegaCore Function User Guide
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