参数资料
型号: IP-SRAM/QDRII
厂商: Altera
文件页数: 63/68页
文件大小: 0K
描述: IP QDRII SRAM CONTROLLER
标准包装: 1
系列: *
类型: MegaCore
功能: QDRII SRAM 控制器
许可证: 初始许可证
Functional Description
Table 3–9 shows the local bus width parameter (only available with burst
length of four).
Table 3–9. Local Bus Width Parameters
Parameter
Value
Description
Local bus w idth
Narro w mode Narro w mode is t w ice the w idth of
or w ide mode the memory; w ide mode is four
times the w idth of the memory.
Table 3–10 shows the memory interface parameters.
Table 3–10. Memory Interface Parameters
Parameter
Device w idth
Device depth
Use altddio pin
Value
1 to 4
1 to 2
On or off
Description
Specifies the number of devices to
increase the w idth of the data bus.
Choose 2 to double the memory
space.
When turned on altddio outputs
generate the clock outputs. Turn off
to use dedicated PLL outputs to
generate the clocks, w hich is
recommended for HardCopy II
devices.
Board & Controller
Table 3–11 shows the pipelining parameters.
Table 3–11. Pipelining Parameters
Parameter
Number of pipeline
registers on address,
command, and data
outputs
Number of pipeline
registers on read data
Value
0 to 4
0 to 4
Description
You can choose 1, 2, or 3 pipeline registers bet w een the memory
controller and the address, command, and data outputs. These
registers help to achieve the required performance at higher
frequencies.
You can choose 1, 2, or 3 pipeline registers bet w een the memory
controller and the read data input. These registers help to achieve the
required performance at higher frequencies.
Altera Corporation
MegaCore Version 9.1 3–31
November 2009
QDRII SRAM Controller MegaCore Function User Guide
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