参数资料
型号: IP-SRAM/QDRII
厂商: Altera
文件页数: 6/68页
文件大小: 0K
描述: IP QDRII SRAM CONTROLLER
标准包装: 1
系列: *
类型: MegaCore
功能: QDRII SRAM 控制器
许可证: 初始许可证
Features
Table 1–2 shows the level of support offered by the QDRII SRAM
Controller MegaCore function to each Altera device family.
Table 1–2. Device Family Support
Device Family
HardCopy ? II
Stratix ?
Stratix II
Stratix II GX
Stratix GX
Other device families (1)
Note to Table 1–2 :
Preliminary
Full
Full
Full
Full
No support
Support
(1)
For more information on support for Stratix III or Stratix IV devices, contact
Altera.
Features
Support for burst of two and four memory type
Support for 8-, 18-, and 36-bit QDRII interfaces
Support for two-times and four-times data width on the local side
(four-times for burst of four only)
Operates at 300 MHz for QDRII and QDRII+ SRAM
Automatic concatenation of consecutive reads and writes (narrow
local bus width mode only)
Easy-to-use IP Toolbench interface
IP functional simulation models for use in Altera-supported VHDL
and Verilog HDL simulators
Support for OpenCore Plus evaluation
General
Description
The QDRII SRAM Controller MegaCore function provides an easy-to-use
interface to QDRII SRAM modules. The QDRII SRAM Controller ensures
that the placement and timing are in line with QDRII specifications.
The QDRII SRAM Controller is optimized for Altera Stratix series. The
advanced features available in these devices allow you to interface
directly to QDRII SRAM devices.
Figure 1–1 shows a system-level diagram including the example design
that the QDRII SRAM Controller MegaCore function creates for you.
1–2 MegaCore Version 9.1
Altera Corporation
QDRII SRAM Controller MegaCore Function User Guide
November 2009
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