参数资料
型号: IP-SRAM/QDRII
厂商: Altera
文件页数: 46/68页
文件大小: 0K
描述: IP QDRII SRAM CONTROLLER
标准包装: 1
系列: *
类型: MegaCore
功能: QDRII SRAM 控制器
许可证: 初始许可证
Interfaces & Signals
Figure 3–10. Write—Burst of Four (Narrow Mode)
avl_clk
avl_write
avl_data_wr[35:0]
avl_adr_wr[19:0]
avl_wait_request_wr
avl_clock_wr
system_clk
00010002
0002
00030004
0003
qdrii_d[17:0]
0001
0002
0003
0004
qdrii_a[19:0]
qdrii_bwsn[1:0]
0002
00
qdrii_wpsn
This section does not illustrate the burst of two example, because you can
transfer any data at any address in every Avalon clock cycle. The timing
of the qdrii_a signal is different, refer to Figure 3–7 on page 3–11 .
Bursts with Pauses
There are no pauses when using a burst of two memories. For the burst of
four, there are some pauses (depending on the mode). In narrow mode, if
the transfers are to consecutive addresses all the time, no pause occurs. If
the transfers are to non-consecutive addresses, a pause may occur, refer
to Figure 3–11 on page 3–15 . a pause occurs only in the following
conditions:
A one-cycle write to address <a> followed straight away by a two-
cycle transfer to addresses <b> and <b + 1>
The second half of the transfer to <b> is paused for a clock cycle
3–14 MegaCore Version 9.1
Altera Corporation
QDRII SRAM Controller MegaCore Function User Guide
November 2009
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