参数资料
| 型号： | IP-SRAM/QDRII |
| 厂商： | Altera |
| 文件页数： | 29/68页 |
| 文件大小： | 0K |
| 描述： | IP QDRII SRAM CONTROLLER |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | QDRII SRAM 控制器 |
| 许可证： | 初始许可证 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页当前第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页
Getting Started
To edit the example PLL, follow these steps:
1.
2.
3.
4.
5.
Choose MegaWizard Plug-In Manager (Tools menu).
Select Edit an existing custom megafunction variation and click
Next .
In your Quartus II project directory, for VHDL choose
qdrii_pll_ < device name > .vhd ; for Verilog HDL choose
qdrii_pll_ < device name > .v .
Click Next .
Edit the PLL parameters in the altpll MegaWizard Plug-In.
f
For more information on the altpll megafunction, refer to the
Quartus II Help or click Documentation in the altpll MegaWizard
Plug-In.
Compile the
Example Design
Before the Quartus II software compiles the example design it runs the IP
Toolbench-generated Tcl constraints script, auto_add_constraints.tcl .
The auto_add_qdrii_constraints.tcl script calls the
add_constraints_for_ <variation name> .tcl script for each variation in your
design. The add_constraints_for_ <variation name> .tcl script checks for
any previously added constraints, removes them, and then adds
constraints for that variation.
The constraints script analyzes and elaborates your design, to
automatically extract the hierarchy to your variation. To prevent the
constraints script analyzing and elaborating your design, turn on Enable
hierarchy control in the wizard, and enter the correct hierarchy path to
your data path (refer to step 13 on page 2–6 ).
When the constraints script runs, it creates another script,
remove_constraints_for_ <variation name> .tcl , which you can use to
remove the constraints from your design.
To compile the example instance, follow these steps:
1.
Optional . Enable TimeQuest Timing Analyzer.
a.
On the Assignments menu click Settings , expand Timing
Analysis Settings , and select Use TimeQuest Timing
Analyzer .
Altera Corporation
MegaCore Version 9.1 2–19
November 2009
QDRII SRAM Controller MegaCore Function User Guide
相关PDF资料 |
PDF描述 |
|---|---|
| IP-VITERBI/SS | IP VITERBI LOW-SPEED |
| IP4220CZ6,125 | IC USB DUAL ESD PROTECT 6TSOP |
| IPA-66-1-600-10.0-A-01-T | CIRC BRKR 10A 2POLE SCREW TERM |
| IPR-CSC | IP COLOR SPACE CONVERTER RENEW |
| IPR-ED8B10B | IP 8B10B ENCODER/DECODER RENEW |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IPSR-AXIBFM | 功能描述:开发软件 Mentor Graphics AXI Verification RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPSR-BASE | 功能描述:开发软件 IP Base Suite MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPSR-EMBEDDED | 功能描述:开发软件 Embedded IP Suite MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPSR-VIDEO | 功能描述:开发软件 Video & Image Proc MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPSR-WMD | 功能描述:IP WIRELSS MOD/DEMOD SUITE RENEW RoHS:否 类别:编程器，开发系统 >> 软件 系列:* 标准包装:1 系列:ISE® 设计套件 类型:订阅 适用于相关产品:Xilinx FPGAs 其它名称:Q4986209T1081384 |
发布紧急采购，3分钟左右您将得到回复。