参数资料
| 型号： | IP-SRAM/QDRII |
| 厂商： | Altera |
| 文件页数： | 65/68页 |
| 文件大小： | 0K |
| 描述： | IP QDRII SRAM CONTROLLER |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | QDRII SRAM 控制器 |
| 许可证： | 初始许可证 |
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Functional Description
Project Settings
Table 3–15 shows the example settings.
Table 3–15. Example Settings
Parameter
Description
Automatically apply QDR When this option is turned on, the next time you compile, the Quartus II soft w are
SRAM controller-specific automatically runs the add constraints script. Turn off this option if you do not w ant
constraints to the
Quartus II project
Update the example
design file that
instantiates the QDRII
SRAM controller
the script to run automatically.
When this option is turned on, IP Toolbench parses and updates the example design
file. It only updates sections that are bet w een the follo w ing markers:
<<START MEGAWIZARD INSERT <tagname>
<<END MEGAWIZARD INSERT <tagname>
variation
If you edit the example design file, ensure that your changes are outside of the
markers or remove the markers. Once you remove the markers, you must keep the
file updated, because IP Toolbench can no longer update the file.
Update example design
system PLL
When this option is turned on, IP Toolbench automatically over w rites the PLL.Turn off
this option, if you do not w ant the w izard to over w rite the PLL. The first time you
create a custom variation, you must turn on Update example design system PLL .
Table 3–16 shows the variation path parameters.
Table 3–16. Variation Path Parameters
Parameter
Enable hierarchy control
Hierarchy path to
variation
Description
The constraints script analyzes your design, to automatically extract the hierarchy to
your variation. To prevent the constraints script analyzing your design, turn on
Enable hierarchy control , and enter the correct hierarchy path to your controller.
The hierarchy path is the path to your QDRII SRAM controller, minus the top-level
name. The hierarchy entered in the w izard must match your design, because the
constraints scripts rely on this path for correct operation.
Table 3–17 shows the pin prefixes parameter.
Table 3–17. Pin Prefixes
Parameter
Prefix all QDRII SRAM
pins w ith
Description
This string prefixes the pin names for the FPGA pins that are connected to the QDRII
SRAM controller.
Altera Corporation
MegaCore Version 9.1 3–33
November 2009
QDRII SRAM Controller MegaCore Function User Guide
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