参数资料
| 型号： | IP-SRAM/QDRII |
| 厂商： | Altera |
| 文件页数： | 39/68页 |
| 文件大小： | 0K |
| 描述： | IP QDRII SRAM CONTROLLER |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | QDRII SRAM 控制器 |
| 许可证： | 初始许可证 |
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Functional Description
Clock Generator
The clock generator generates the memory signals k and kn . The clocks
are derived from the PLL-generated clock and are shifted by 90 ? to the
system clock.
Address & Command Output Registers
The address and command output registers generate the following
outputs:
■
■
■
■
Address
Read
Write
Write byte enable
There is one set of signals per device on a board.
With more than one device on a board, a suffix indicates the width
position and depth position. The width can be anything up to what the
device supports (for example, you can make a 72-bit interface out of four
18-bit interfaces). The depth is limited to 2.
For a device depth of two, you must connect the reads and writes to each
device. The top address bit going into the address command top-level file
is a device select, which selects device 0 or 1 by setting the read and write
of the unused device to 1.
Write Registers
The write registers comprise write I/O blocks going to the memory. For
each memory in width, the controller creates a data bus. For a device
depth of two, the controller shares the data bus between the two devices.
The Capture Group Module
The capture group module comprises the following elements:
■
■
CQ/CQN group module
Read capture registers
The controller uses the 90 ?? shifted cq and cqn clocks for the capture
registers of the q bus.
When captured, the controller synchronizes the two words on a double
width bus.
Altera Corporation
MegaCore Version 9.1 3–7
November 2009
QDRII SRAM Controller MegaCore Function User Guide
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