参数资料
型号: IP-SRAM/QDRII
厂商: Altera
文件页数: 45/68页
文件大小: 0K
描述: IP QDRII SRAM CONTROLLER
标准包装: 1
系列: *
类型: MegaCore
功能: QDRII SRAM 控制器
许可证: 初始许可证
Functional Description
Figure 3–9. Write—Burst of Four (Wide Mode)
avl_clk
avl_write
avl_data_wr[35:0]
avl_adr_wr[19:0]
avl_wait_request_wr
avl_clock_wr
system_clk
01020304
0001
qdrii_d[17:0]
01
02
03
04
qdrii_a[19:0]
qdrii_bwsn[1:0]
0001
00
qdrii_wpsn
Bursts
Bursts are only possible on the Avalon side in the burst of two mode,
where you can transfer data every clock cycle and in bursts of four
(narrow mode). It is not possible in the burst of four (wide mode), because
it takes two QDRII SRAM clock cycles to transfer one Avalon clock cycle
of data.
Figure 3–10 on page 3–14 shows the burst of four (narrow mode). When
two write requests are sent on the Avalon interface at consecutive
addresses, the controller automatically concatenates them and transfers
them to the QDRII SRAM, if the first one is an even address. If more data
is coming in the following cycle, it is also sent straight away, without any
pause.
Altera Corporation
MegaCore Version 9.1 3–13
November 2009
QDRII SRAM Controller MegaCore Function User Guide
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