参数资料
型号: IP-SRAM/QDRII
厂商: Altera
文件页数: 7/68页
文件大小: 0K
描述: IP QDRII SRAM CONTROLLER
标准包装: 1
系列: *
类型: MegaCore
功能: QDRII SRAM 控制器
许可证: 初始许可证
About This MegaCore Function
Figure 1–1. QDRII SRAM Controller System-Level Diagram
Example Design
Control Logic
Local
(Encrypted)
Pass
or Fail
Example
Driver
Interface
Clock
System
PLL
Resynchronization
& Pipeline Logic
QDRII
SRAM
Interface
QDRII SRAM
(Clear Text)
DLL (1)
Fedback
Clock
Datapath
(Clear Text)
PLL (2)
QDRII SRAM Controller
Notes to Figure 1–1 :
(1)
Optional, for Stratix II devices only.
(2)
Non-DQS mode only.
The IP Toolbench-generated example design instantiates a phase-locked
loop (PLL), an optional DLL (for Stratix II devices only), an example
driver, and your QDRII SRAM Controller custom variation. The example
design is a fully-functional example design that can be simulated,
synthesized, and used in hardware. The example driver is a self-test
module that issues read and write commands to the controller and checks
the read data to produce the pass/fail and test complete signals.
You can replace the QDRII SRAM controller encrypted control logic in
the example design with your own custom logic, which allows you to use
the Altera clear-text resynchronization and pipeline logic and datapath
with your own control logic.
OpenCore Plus Evaluation
With Altera’s free OpenCore Plus evaluation feature, you can perform
the following actions:
Altera Corporation
MegaCore Version 9.1 1–3
November 2009
QDRII SRAM Controller MegaCore Function User Guide
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