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| 型号： | ISP1561BM,557 |
| 厂商： | ST-ERICSSON |
| 元件分类： | 总线控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP128 |
| 封装： | 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-128 |
| 文件页数： | 19/103页 |
| 文件大小： | 457K |
| 代理商： | ISP1561BM,557 |
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ISP1561_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 5 March 2007
22 of 103
NXP Semiconductors
ISP1561
HS USB PCI Host Controller
8.2.1.18
Interrupt Pin register (address: 3Dh)
This 1-byte register is use to specify which interrupt pin the device or device function uses.
The bit description is given in Table 22.
Devices or functions that do not use an interrupt pin must put a logic 0 in this register.
8.2.1.19
MIN_GNT and MAX_LAT registers (address: 3Eh and 3Fh)
The Minimum Grant (MIN_GNT) and Maximum Latency (MAX_LAT) registers are used to
specify the desired settings of the device for latency timer values. For both registers, the
value species a period of time in units of 250 ns. Values of 0 indicates that the device has
no major requirements for the settings of latency timers.The MIN_GNT register bit
description is given in Table 23.
[1]
X is 01h for OHCI1 and OHCI2; X is 02h for EHCI.
The MAX_LAT register bit description is given in Table 24.
[1]
X is 2Ah for OHCI1 and OHCI2; X is 10h for EHCI.
8.2.1.20
TRDY Timeout register (R/W: 40h)
The default and recommended value is 00h, TRDY time-out disabled. This value can,
however, be modied. It is an implementation-specic register, and not a standard PCI
conguration register.
The TRDY timer is 13 bits: the lower 5 bits are xed as logic 0 and the upper 8 bits are
determined by the TRDY time-out register value. The time-out is calculated by multiplying
the 13-bit timer with the PCICLK cycle time.
This register determines the delay for the UE bit setting if a target does not assert its
TDRY signal.
8.2.1.21
Retry Timeout register (R/W: 41h)
The default value is 80h. This value can, however, be modied. Programming this register
as 00h means that retry time-out is disabled. This is an implementation-specic register,
and not a standard PCI conguration register.
The time-out is determined by multiplying the register value with the PCICLK cycle time.
This register determines the delay to set the UE bit if a RETRY time-out occurs.
Table 22.
Interrupt Pin register: bit description
Bit
Symbol
Access
Value
Description
7 to 0
IP[7:0]
R/W
01h
Interrupt Pin: INTA# is the default interrupt pin used by the ISP1561.
Table 23.
MIN_GNT register: bit description
Bit
Symbol
Access
Value
Description
7 to 0
MIN_GNT[7:0] R
X[1]
MIN_GNT: It is used to specify how long a burst period the device needs,
assuming a clock rate of 33 MHz.
Table 24.
MAX_LAT register: but description
Bit
Symbol
Access
Value
Description
7 to 0
MAX_LAT[7:0]
R
X[1]
MAX_LAT: It is used to specify how often the device needs to gain
access to the PCI bus.
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相关代理商/技术参数 |
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| ISP1562BE | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Hi-Speed USB PCI host controller |
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