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| 型号： | ISP1561BM,557 |
| 厂商： | ST-ERICSSON |
| 元件分类： | 总线控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP128 |
| 封装： | 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-128 |
| 文件页数： | 39/103页 |
| 文件大小： | 457K |
| 代理商： | ISP1561BM,557 |
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ISP1561_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 5 March 2007
40 of 103
NXP Semiconductors
ISP1561
HS USB PCI Host Controller
11.1.4 HcInterruptStatus register (address: content of the base address register +
0Ch)
This is a 4-byte register that provides the status of the events that cause hardware
interrupts. The bit allocation of the register is given in Table 49. When an event occurs, the
Host Controller sets the corresponding bit in this register. When a bit becomes set, a
hardware interrupt is generated if the interrupt is enabled in the HcInterruptEnable register
(see Table 51) and the MIE (Master Interrupt Enable) bit is set. The HCD may clear
specic bits in this register by writing logic 1 to the bit positions to be cleared. The HCD
may not set any of these bits. The Host Controller does not clear the bit.
1
CLF
Control List Filled: This bit is used to indicate whether there are any TDs
on the control list. It is set by the HCD whenever it adds a TD to an ED in
the control list.
When the Host Controller begins to process the head of the control list, it
checks CLF. If CLF is logic 0, the Host Controller does not need to
process the control list. If Control-Filled (CF) is logic 1, the Host Controller
must start processing the control list and set CLF to logic 0. If the Host
Controller nds a TD on the list, then the Host Controller must set CLF to
logic 1, causing the control list processing to continue. If no TD is found
on the control list, and if the HCD does not set CLF, then CLF is still
logic 0 when the Host Controller completes processing the control list and
the control list processing stops.
0
HCR
Host Controller Reset: This bit is set by the HCD to initiate a software
reset of the Host Controller. Regardless of the functional state of the Host
Controller, it moves to the USBSUSPEND state in which most of the
operational registers are reset, except those stated otherwise; for
example, the IR (Interrupt Routing) eld of HcControl, and no host bus
accesses are allowed. This bit is cleared by the Host Controller on
completing the reset operation. The reset operation must be completed
within 10
s. This bit, when set, must not cause a reset to the root hub
and no subsequent reset signaling must be asserted to its downstream
ports.
Table 48.
HcCommandStatus register: bit description …continued
Bit
Symbol
Description
Table 49.
HcInterruptStatus register: bit allocation
Bit
31
30
29
28
27
26
25
24
Symbol
reserved
OC
reserved
Reset
00000000
Access
-
R/W
------
Bit
23
22
21
20
19
18
17
16
Symbol
reserved
Reset
00000000
Access
--------
Bit
15
14
13
12
11
10
9
8
Symbol
reserved
Reset
00000000
Access
--------
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