参数资料
型号: ISP1561BM,557
厂商: ST-ERICSSON
元件分类: 总线控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封装: 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-128
文件页数: 43/103页
文件大小: 457K
代理商: ISP1561BM,557
ISP1561_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 5 March 2007
44 of 103
NXP Semiconductors
ISP1561
HS USB PCI Host Controller
11.1.7 HcHCCA register (address: content of the base address register + 18h)
The HcHCCA register contains the physical address of Host Controller Communication
Area (HCCA). The bit allocation is given in Table 55. The HCD determines alignment
restrictions by writing all 1s to HcHCCA and reading the content of HcHCCA. The
alignment is evaluated by examining the number of zeroes in the lower order bits. The
minimum alignment is 256 bytes; therefore, bits 0 through 7 will always return logic 0
when read. This area is used to hold control structures and the Interrupt table that are
accessed by both the Host Controller and the HCD.
Table 54.
HcInterruptDisable register: bit description
Bit
Symbol
Description
31
MIE
Master Interrupt Enable:
0 — Ignore
1 — Disables interrupt generation because of events specied in other
bits of this register.
This eld is set after a hardware or software reset. Interrupts are
disabled.
30
OC
Ownership Change:
0 — Ignore
1 — Disables interrupt generation because of ownership change
29 to 7
-
reserved
6
RHSC
Root Hub Status Change:
0 — Ignore
1 — Disables interrupt generation because of root hub status change
5
FNO
Frame Number Overow:
0 — Ignore
1 — Disables interrupt generation because of frame number overow
4UE
Unrecoverable Error:
0 — Ignore
1 — Disables interrupt generation because of unrecoverable error
3RD
Resume Detect:
0 — Ignore
1 — Disables interrupt generation because of resume detect
2SF
Start-of-Frame:
0 — Ignore
1 — Disables interrupt generation because of Start-of-Frame
1
WDH
HcDoneHead Write-back:
0 — Ignore
1 — Disables interrupt generation because of HcDoneHead
write-back
0SO
Scheduling Overrun:
0 — Ignore
1 — Disables interrupt generation because of scheduling overrun
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