参数资料
型号: ISP1561BM,557
厂商: ST-ERICSSON
元件分类: 总线控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封装: 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-128
文件页数: 66/103页
文件大小: 457K
代理商: ISP1561BM,557
ISP1561_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 5 March 2007
65 of 103
NXP Semiconductors
ISP1561
HS USB PCI Host Controller
11.2.4 HceStatus register (address: content of the base address register + 10Ch)
The contents of the HceStatus register are returned on an I/O read of port 64h when
emulation is enabled. Reads and writes of port 60h, and writes to port 64h can cause
changes in this register. Emulation software can directly access this register through its
memory address in the Host Controller’s operational register space. Accessing this
register through its memory address produces no side effects. Table 95 contains the bit
allocation.
Table 94.
HceOutput register: bit description
Bit
Symbol
Description
31 to 8
-
reserved
7 to 0
OUT_DATA[7:0] Output Data: This register holds the data that is returned when an I/O
read of port 60h is requested by application software.
Table 95.
HceStatus register: bit allocation
Bit
31
30
29
28
27
26
25
24
Symbol
reserved
Reset
00000000
Access
--------
Bit
23
22
21
20
19
18
17
16
Symbol
reserved
Reset
00000000
Access
--------
Bit
15
14
13
12
11
10
9
8
Symbol
reserved
Reset
00000000
Access
--------
Bit
7
6
5
4
3
2
1
0
Symbol
PARITY
TIMEOUT
AUX_OUT
_FULL
INH_SW
CMD_DATA
FLAG
IN_FULL
OUT_FULL
Reset
00000000
Access
R/W
Table 96.
HceStatus register: bit description
Bit
Symbol
Description
31 to 8 -
reserved
7
PARITY
Parity: This bit indicates parity error on keyboard and mouse data.
6
TIMEOUT
Time-out: This bit indicates a time-out.
5
AUX_OUT_
FULL
Auxiliary Output Full: IRQ12 is asserted whenever this bit is set to
logic 1, OUT_FULL (Output Full) is set to logic 1, and the IRQEN bit is set.
4
INH_SW
Inhibit Switch: This bit reects the state of the keyboard inhibit switch. If
set, the keyboard is active.
3
CMD_DATA
Cmd Data: The Host Controller sets this bit to logic 0 on an I/O write to
port 60h and to logic 1 on an I/O write to port 64h.
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