- 您现在的位置：买卖IC网 > PDF目录67723 > ISP1561BM,557 (ST-ERICSSON) UNIVERSAL SERIAL BUS CONTROLLER, PQFP128 PDF资料下载
参数资料
| 型号： | ISP1561BM,557 |
| 厂商： | ST-ERICSSON |
| 元件分类： | 总线控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP128 |
| 封装： | 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-128 |
| 文件页数： | 73/103页 |
| 文件大小： | 457K |
| 代理商： | ISP1561BM,557 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页当前第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页
ISP1561_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 5 March 2007
71 of 103
NXP Semiconductors
ISP1561
HS USB PCI Host Controller
6
IAAD
Interrupt on Asynchronous Advance Doorbell: This bit is used as a
doorbell by software to notify the Host Controller to issue an interrupt the next
time it advances the asynchronous schedule. Software must write logic 1 to
this bit to ring the doorbell. When the Host Controller has evicted all
appropriate cached schedule states, it sets the IAA (Interrupt on
Asynchronous Advance) status bit in the USBSTS register. If the IAAE
(Interrupt on Asynchronous Advance Enable) bit in the USBINTR register is
logic 1, then the Host Controller will assert an interrupt at the next interrupt
threshold. The Host Controller sets this bit to logic 0 after it sets IAA (Interrupt
on Asynchronous Advance) status bit in the USBSTS register. Software must
not set this bit when the asynchronous schedule is inactive because this
results in an undened value.
5
ASE
Asynchronous Schedule Enable: Default = 0. This bit controls whether the
Host Controller skips processing the asynchronous schedule.
0 — Do not process the asynchronous schedule
1 — Use the ASYNCLISTADDR register to access the asynchronous
schedule
4
PSE
Periodic Schedule Enable: Default = 0. This bit controls whether the Host
Controller skips processing the periodic schedule.
0 — Do not process the periodic schedule
1 — Use the PERIODICLISTBASE register to access the periodic schedule
3 to 2
FLS[1:0] Frame List Size: Default = 00b. This eld is read and write only if PFLF (bit 1)
in the HCCPARAMS register is set to logic 1. This eld species the size of the
frame list. The size the frame list controls which bits in the Frame Index
register must be used for the frame list current index.
00b — 1024 elements (4096 bytes)
01b — 512 elements (2048 bytes)
10b — 256 elements (1024 bytes) for small environments
11b — reserved
1HC
RESET
Host Controller Reset: This control bit is used by the software to reset the
Host Controller. The effects of this on Root Hub registers are similar to a chip
hardware reset. Setting this bit causes the Host Controller to reset its internal
pipelines, timers, counters, state machines, and so on, to their initial values.
Any transaction currently in progress on USB is immediately terminated. A
USB reset is not driven on downstream ports. This reset does not affect PCI
Conguration registers. All operational registers, including port registers and
port state machines, are set to their initial values. Port ownership reverts to the
companion Host Controller(s). The software must re-initialize the Host
Controller to return it to an operational state. This bit is cleared by the Host
Controller when the reset process is complete. Software cannot terminate the
reset process early by writing logic 0 to this register. Software must check the
HCH (HC Halted) bit in the USBSTS register is logic 0 before setting this bit.
Attempting to reset an actively running Host Controller results in undened
behavior.
0RS
Run/Stop: 1 = Run. 0 = Stop. When set, the Host Controller executes the
schedule. The Host Controller continues execution as long as this bit is set.
When this bit is cleared, the Host Controller completes the current and active
transactions in the USB pipeline, and then halts. The HCH (HC Halted) bit in
the USBSTS register indicates when the Host Controller has nished the
transaction and has entered the stopped state. Software must check HCH (HC
Halted) in the USBSTS register is logic 1, before setting this bit.
Table 104. USBCMD register: bit description …continued
Bit
Symbol
Description
相关PDF资料 |
PDF描述 |
|---|---|
| ISP1561BM,557 | UNIVERSAL SERIAL BUS CONTROLLER, PQFP128 |
| ISP1563BM | UNIVERSAL SERIAL BUS CONTROLLER, PQFP100 |
| ISP1563BM,557 | UNIVERSAL SERIAL BUS CONTROLLER, PQFP100 |
| ISP1564ET,551 | PCI BUS CONTROLLER, PBGA100 |
| ISP1582BS,557 | UNIVERSAL SERIAL BUS CONTROLLER, PQCC56 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ISP1561BMGA | 功能描述:IC USB HOST CTRL HI-SPD 128LQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 控制器 系列:- 标准包装:4,900 系列:- 控制器类型:USB 2.0 控制器 接口:串行 电源电压:3 V ~ 3.6 V 电流 - 电源:135mA 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:36-VFQFN 裸露焊盘 供应商设备封装:36-QFN（6x6） 包装:* 其它名称:Q6396337A |
| ISP1561BMGE | 功能描述:IC USB PCI HOST CTRLR 128-LQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 控制器 系列:- 标准包装:4,900 系列:- 控制器类型:USB 2.0 控制器 接口:串行 电源电压:3 V ~ 3.6 V 电流 - 电源:135mA 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:36-VFQFN 裸露焊盘 供应商设备封装:36-QFN（6x6） 包装:* 其它名称:Q6396337A |
| ISP1561BMUM | 功能描述:IC USB HOST CTRL HI-SPD 128LQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 控制器 系列:- 标准包装:4,900 系列:- 控制器类型:USB 2.0 控制器 接口:串行 电源电压:3 V ~ 3.6 V 电流 - 电源:135mA 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:36-VFQFN 裸露焊盘 供应商设备封装:36-QFN（6x6） 包装:* 其它名称:Q6396337A |
| ISP1562 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Hi-Speed USB PCI host controller |
| ISP1562BE | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Hi-Speed USB PCI host controller |
发布紧急采购，3分钟左右您将得到回复。