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参数资料
型号： ISP1561BM,557
厂商： ST-ERICSSON
元件分类： 总线控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封装： 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-128
文件页数： 25/103页
文件大小： 457K
代理商： ISP1561BM,557
ISP1561_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 5 March 2007
28 of 103
NXP Semiconductors
ISP1561
HS USB PCI Host Controller
8.2.3.5
PMCSR_BSE register (address: value read from address 34h + 6h)
The PMCSR PCI-to-PCI Bridge Support Extensions (PMCSR_BSE) register supports PCI
bridge-specic functionality and is required for all PCI-to-PCI bridges. The bit allocation of
this register is given in Table 38.
[1]
Internally hardwired.
1 to 0
PS[1:0]
Power State: This two-bit eld is used to determine the current power
state of the EHCI function and to set the function into a new power
state. The denition of the eld values is given as:
00b — for D0
01b — for D1
10b — for D2
11b — for D3hot
If the software attempts to write an unsupported, optional state to this
eld, the write operation must complete normally on the bus; however,
the data is discarded and no status change occurs.
Table 37.
PMCSR register: bit description …continued
Bit
Symbol
Description
Table 38.
PMCSR_BSE register: bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
BPCC_EN
B2_B3#
reserved
Reset
RRRRRRRR
Access
0[1]
000000
Table 39.
PMCSR_BSE register: bit description
Bit
Symbol
Description
7
BPCC_EN
Bus Power or Clock Control Enable
1 — Indicates that the bus power or clock control mechanism as dened in
Table 40 is enabled.
0 — Indicates that the bus power or control policies as dened in Table 40
are disabled.
When the bus power or clock control mechanism is disabled, the bridge’s
PMCSR PS (Power State) eld cannot be used by the system software to
control the power or clock of the bridge’s secondary bus.
6
B2_B3#
B2 or B3 support for D3hot: The state of this bit determines the action that
is to occur as a direct result of programming the function to D3hot.
1 — Indicates that when the bridge function is programmed to D3hot, its
secondary bus’s PCI clock will be stopped (B2).
0 — Indicates that when the bridge function is programmed to D3hot, its
secondary bus will have its power removed (B3).
This bit is only meaningful if bit 7 (BPCC_EN) is logic 1.
5 to 0
-
reserved
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