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| 型号： | ISP1561BM,557 |
| 厂商： | ST-ERICSSON |
| 元件分类： | 总线控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP128 |
| 封装： | 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-128 |
| 文件页数： | 40/103页 |
| 文件大小： | 457K |
| 代理商： | ISP1561BM,557 |
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ISP1561_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 5 March 2007
41 of 103
NXP Semiconductors
ISP1561
HS USB PCI Host Controller
11.1.5 HcInterruptEnable register (address: content of the base address register +
10h)
Each enable bit in the HcInterruptEnable register corresponds to an associated interrupt
bit in the HcInterruptStatus register. The HcInterruptEnable register is used to control
which events generate a hardware interrupt. If the following conditions occur:
A bit is set in the HcInterruptStatus register.
The corresponding bit in the HcInterruptEnable register is set.
The MIE (Master Interrupt Enable) bit is set.
Bit
7
6
5
4
3
2
1
0
Symbol
reserved
RHSC
FNO
UE
RD
SF
WDH
SO
Reset
00000000
Access
-
R/W
Table 50.
HcInterruptStatus register: bit description
Bit
Symbol
Description
31
-
reserved
30
OC
Ownership Change: This bit is set by the Host Controller when HCD
sets the OCR (Ownership Change Request) eld in
HcCommandStatus. This event, when unmasked, will always
immediately generate a System Management Interrupt (SMI). This bit
is forced to logic 0 when the SMI# pin is not implemented.
29 to 7
-
reserved
6
RHSC
Root Hub Status Change: This bit is set when the content of
HcRhStatus or the content of any of
HcRhPortStatus[NumberofDownstreamPort] has changed.
5
FNO
Frame Number Overow: This bit is set when the Most Signicant Bit
(MSB) of HcFmNumber (bit 15) changes value, or after the
HccaFrameNumber is updated.
4UE
Unrecoverable Error: This bit is set when the Host Controller detects
a system error not related to USB. The Host Controller must not
proceed with any processing nor signaling before the system error is
corrected. The HCD clears this bit after the Host Controller is reset.
3RD
Resume Detected: This bit is set when the Host Controller detects
that a device on the USB is asserting resume signaling. It is the
transition from no resume signaling to resume signaling causing this
bit to be set. This bit is not set when the HCD sets the USBRESUME
state.
2SF
Start-of-Frame: At the start of each frame, this bit is set by the Host
Controller and an SOF token is generated at the same time.
1
WDH
Write-back Done Head: This bit is immediately set after the Host
Controller has written HcDoneHead to HccaDoneHead. Further,
updates of HccaDoneHead occur only after this bit is cleared. The
HCD must only clear this bit after it has saved the content of
HccaDoneHead.
0SO
Scheduling Overrun: This bit is set when USB schedules for current
frame overruns and after the update of HccaFrameNumber. A
scheduling overrun causes the SOC (Scheduling Overrun Count) of
HcCommandStatus to be incremented.
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相关代理商/技术参数 |
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| ISP1561BMUM | 功能描述:IC USB HOST CTRL HI-SPD 128LQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 控制器 系列:- 标准包装:4,900 系列:- 控制器类型:USB 2.0 控制器 接口:串行 电源电压:3 V ~ 3.6 V 电流 - 电源:135mA 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:36-VFQFN 裸露焊盘 供应商设备封装:36-QFN（6x6） 包装:* 其它名称:Q6396337A |
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| ISP1562BE | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Hi-Speed USB PCI host controller |
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