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参数资料
型号： ISP1561BM,557
厂商： ST-ERICSSON
元件分类： 总线控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封装： 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-128
文件页数： 58/103页
文件大小： 457K
代理商： ISP1561BM,557
ISP1561_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 5 March 2007
58 of 103
NXP Semiconductors
ISP1561
HS USB PCI Host Controller
11.1.22 HcRhPortStatus[1:4] register (address: content of the base address
register + 54h)
The HcRhPortStatus[1:4] register is used to control and report port events on a per-port
basis. NumberofDownstreamPort represents the number of HcRhPortStatus registers that
are implemented in hardware. The lower word reects the port status. The upper word
reects status change bits. Some status bits are implemented with special write behavior.
If a transaction, token through handshake, is in progress when a write to change port
status occurs, the resulting port status change is postponed until the transaction
completes. Always write logic 0 to the reserved bits. The bit allocation of the register is
given in Table 85.
14 to 2
-
reserved
1
OCI
Overcurrent Indicator: This bit reports overcurrent conditions when global
reporting is implemented. When set, an overcurrent condition exists. When
cleared, all power operations are normal. If the per-port overcurrent protection
is implemented, this bit is always logic 0.
0
LPS
On read Local Power Status: The root hub does not support the local power
status feature. Therefore, this bit is always read as logic 0.
On write Clear Global Power: In global power mode (Power Switching
Mode = 0), logic 1 is written to this bit to turn off power to all ports (clear Port
Power Status). In per-port power mode, it clears Port Power Status only on
ports whose Port Power Control Mask bit is not set. Writing logic 0 has no
effect.
Table 84.
HcRhStatus register: bit description …continued
Bit
Symbol Description
Table 85.
HcRhPortStatus[1:4] register: bit allocation
Bit
31
30
29
28
27
26
25
24
Symbol
reserved
Reset
00000000
Access
--------
Bit
23
22
21
20
19
18
17
16
Symbol
reserved
PRSC
OCIC
PSSC
PESC
CSC
Reset
00000000
Access
-
R/W
Bit
15
14
13
12
11
10
9
8
Symbol
reserved
LSDA
PPS
Reset
00000000
Access
------
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
reserved
PRS
POCI
PSS
PES
CCS
Reset
00000000
Access
-
R/W
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