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参数资料
型号： ISP1561BM,557
厂商： ST-ERICSSON
元件分类： 总线控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封装： 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-128
文件页数： 74/103页
文件大小： 457K
代理商： ISP1561BM,557
ISP1561_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 5 March 2007
72 of 103
NXP Semiconductors
ISP1561
HS USB PCI Host Controller
11.4.2 USBSTS register (address: content of the base address register + 10h)
The USB Status (USBSTS) register indicates pending interrupts and various states of the
Host Controller. The status resulting from a transaction on the serial bus is not indicated in
this register. Software clears the register bits by writing ones to them. The bit allocation is
given in Table 105.
Table 105. USBSTS register: bit allocation
Bit
31
30
29
28
27
26
25
24
Symbol
reserved
Reset
00000000
Access
--------
Bit
23
22
21
20
19
18
17
16
Symbol
reserved
Reset
00000000
Access
--------
Bit
15
14
13
12
11
10
9
8
Symbol
ASS
PSSTAT
RECL
HCH
reserved
Reset
00010000
Access
RRRR
----
Bit
7
6
5
4
3
2
1
0
Symbol
reserved
IAA
HSE
FLR
PCD
USB
ERRINT
USBINT
Reset
00000000
Access
-
R
R/W
Table 106. USBSTS register: bit description
Bit
Symbol
Description
31 to 16
-
reserved
15
ASS
Asynchronous Schedule Status: 0 = Default. The bit reports the
current real status of the asynchronous schedule. If this bit is logic 0,
the status of the asynchronous schedule is disabled. If this bit is
logic 1, the status of the asynchronous schedule is enabled. The
Host Controller is not required to immediately disable or enable the
asynchronous schedule when software changes the ASE
(Asynchronous Schedule Enable) bit in the USBCMD register. When
this bit and the ASE (Asynchronous Schedule Enable) bit have the
same value, the asynchronous schedule is either enabled (1) or
disabled (0).
14
PSSTAT
Periodic Schedule Status: 0 = Default. This bit reports the current
status of the periodic schedule. If this bit is logic 0, the status of the
periodic schedule is disabled. If this bit is logic 1, the status of the
periodic schedule is enabled. The Host Controller is not required to
immediately disable or enable the periodic schedule when software
changes the PSE (Periodic Schedule Enable) bit in the USBCMD
register. When this bit and the PSE bit have the same value, the
periodic schedule is either enabled (1) or disabled (0).
13
RECL
Reclamation: 0 = Default. This is a read-only status bit that is used
to detect an empty asynchronous schedule.
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