参数资料
型号: ISP1561BM,557
厂商: ST-ERICSSON
元件分类: 总线控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封装: 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-128
文件页数: 23/103页
文件大小: 457K
代理商: ISP1561BM,557
ISP1561_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 5 March 2007
26 of 103
NXP Semiconductors
ISP1561
HS USB PCI Host Controller
The logic level of the AMB4 pin at power-on determines the default value of PMC
registers. If this pin is connected to VDD as a pull-up, then the ISP1561 supports D3cold (in
the case of notebook design). If this pin is left open or is pulled down, then the ISP1561
does not support D3cold (in the case of PCI add-on card design).
8.2.3.4
PMCSR register (address: value read from address 34h + 4h)
The Power Management Control/Status (PMCSR) register is a 2-byte register used to
manage the power management state of the PCI function, as well as to allow and monitor
Power Management Events (PMEs). The bit allocation of the register is given in Table 36.
8 to 6
AUX_C[2:0]
Auxiliary Current: This three-bit eld reports the VAUX auxiliary
current requirements for the PCI function.
If the Data register is implemented by this function:
A read from this eld needs to return a value of 000b.
The Data register takes precedence over this eld for VAUX
current requirement reporting.
If the PME# generation from D3cold is not supported by the
function (PMC[15] = 0), this eld must return a value of 000b when
read.
For functions that support PME# from D3cold and do not implement
the Data register, bit assignments correspond to the maximum
current required for VAUX are:
111b — 375 mA
110b — 320 mA
101b — 270 mA
100b — 220 mA
011b — 160 mA
010b — 100 mA
001b — 55 mA
000b — 0 (self-powered)
5
DSI
Device Specic Initialization: This bit indicates whether special
initialization of this function is required, beyond the standard PCI
conguration header, before the generic class device driver can
use it.
Remark: This bit is not used by some operating systems. For
example, Microsoft Windows and Windows NT do not use this bit
to determine whether to use D3. Instead, it is determined using
the capabilities of the driver.
Logic 1 indicates that the function requires a device-specic
initialization sequence, following transition to D0 uninitialized state.
4
-
reserved
3
PMI
PME Clock: When this bit is logic 1, it indicates that the function
relies on the presence of the PCI clock for the PME# operation.
When this bit is logic 0, it indicates that no PCI clock is required for
the function to generate PME#. Functions that do not support the
PME# generation in any state must return logic 0 for this eld.
2 to 0
VER[2:0]
Version: A value of 010b indicates that this function complies with
Table 35.
PMC register: bit description …continued
Bit
Symbol
Description
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