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| 型号： | ISP1561BM,557 |
| 厂商： | ST-ERICSSON |
| 元件分类： | 总线控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP128 |
| 封装： | 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-128 |
| 文件页数： | 24/103页 |
| 文件大小： | 457K |
| 代理商： | ISP1561BM,557 |
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ISP1561_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 5 March 2007
27 of 103
NXP Semiconductors
ISP1561
HS USB PCI Host Controller
[1]
Sticky bit, if the function supports PME# from D3cold, then X is indeterminate at the time of initial operating system boot; X is 0 if the
function does not support PME# from D3cold.
Table 36.
PMCSR register: bit allocation
Bit
15
14
13
12
11
10
9
8
Symbol
PMES
DS[1:0]
D_S[3:0]
PMEE
Reset
X[1]
000000
X[1]
Access
R/W
R
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
reserved
PS[1:0]
Reset
00000000
Access
------
R/W
Table 37.
PMCSR register: bit description
Bit
Symbol
Description
15
PMES
PME Status: This bit is set when the function normally asserts the
PME# signal independent of the state of the PME_EN bit. Writing
logic 1 to this bit clears it and causes the function to stop asserting
PME#, if enabled. Writing logic 0 has no effect. This bit defaults to
logic 0, if the function does not support the PME# generation from
D3cold. If the function supports the PME# generation from D3cold, then
this bit is sticky and must be explicitly cleared by the operating system
each time the operating system is initially loaded.
14 to 13
DS[1:0]
Data Scale: This two-bit read-only eld indicates the scaling factor
when interpreting the value of the Data register. The value and
meaning of this eld vary, depending on which data value is selected by
the D_S eld. This eld is a required component of the Data register
(offset 7) and must be implemented, if the Data register is
implemented. If the Data register is not implemented, this eld must
return 00b when PMCSR is read.
12 to 9
D_S[3:0]
Data Select: This four-bit eld selects the data that is reported through
the Data register and the D_S eld. This eld is a required component
of the Data register (offset 7) and must be implemented if the Data
register is implemented. If the Data register is not implemented, this
eld must return 00b when PMCSR is read.
8
PMEE
PME Enabled: Logic 1 allows the function to assert PME#. When it is
logic 0, PME# assertion is disabled. This bit defaults to logic 0 if the
function does not support the PME# generation from D3cold. If the
function supports PME# from D3cold, then this bit is sticky and must
explicitly be cleared by the operating system each time the operating
system is initially loaded. Functions that do not support the PME#
generation from any D-state (that is, PMC[15:11] = 0 0000b), may
hardwire this bit to be read-only always returning logic 0 when read by
system software.
7 to 2
-
reserved
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