参数资料
型号: ISP1561BM,557
厂商: ST-ERICSSON
元件分类: 总线控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封装: 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-128
文件页数: 68/103页
文件大小: 457K
代理商: ISP1561BM,557
ISP1561_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 5 March 2007
67 of 103
NXP Semiconductors
ISP1561
HS USB PCI Host Controller
11.3.2 HCSPARAMS register (address: content of the base address register + 04h)
The Host Controller Structural Parameters (HCSPARAMS) register is a set of elds that
are structural parameters. The bit allocation is given in Table 99.
Table 98.
CAPLENGTH/HCIVERSION register: bit description
Bit
Symbol
Description
31 to 24 -
reserved
23 to 8
HCIVERSION
[15:0]
Host Controller Interface Version Number: It contains a BCD
encoded version number of the interface to which the Host Controller
interface conforms.
7 to 0
CAPLENGTH
[7:0]
Capability Register Length: This is used as an offset. It is added to the
register base to nd the beginning of the operational register space.
Table 99.
HCSPARAMS register: bit allocation
Bit
31
30
29
28
27
26
25
24
Symbol
reserved
Reset
00000000
Access
--------
Bit
23
22
21
20
19
18
17
16
Symbol
DPN[3:0]
reserved
P_INDI
CATOR
Reset
00000000
Access
RRRR
-
R
Bit
15
14
13
12
11
10
9
8
Symbol
N_CC[3:0]
N_PCC[3:0]
Reset
00100010
Access
RRRRRRRR
Bit
7
6
5
4
3
2
1
0
Symbol
PRR
reserved
PPC
N_PORTS[3:0]
Reset
00010100
Access
R
-
RRRRR
Table 100. HCSPARAMS register: bit description
Bit
Symbol
Description
31 to 24
-
reserved
23 to 20
DPN[3:0]
Debug Port Number: This eld identies which of the Host Controller
ports is the debug port. A nonzero value in this eld indicates the
presence of a debug port. The value in this register must not be greater
than N_PORTS.
19 to 17
reserved
16
P_
INDICATOR
Port Indicators: This bit indicates whether the ports support port
indicator control. When this bit is logic 1, the port status and control
registers include a read/writable eld to control the state of the port
indicator.
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