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| 型号： | ISP1561BM,557 |
| 厂商： | ST-ERICSSON |
| 元件分类： | 总线控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP128 |
| 封装： | 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-128 |
| 文件页数： | 64/103页 |
| 文件大小： | 457K |
| 代理商： | ISP1561BM,557 |
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ISP1561_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 5 March 2007
63 of 103
NXP Semiconductors
ISP1561
HS USB PCI Host Controller
11.2.2 HceInput register (address: content of the base address register + 104h)
The HceInput register is a 4-byte register, and the bit allocation is given in Table 91. The
I/O data that is written to ports 60h and 64h is captured in this register, when emulation is
enabled. This register may directly be read or written by accessing it in the Host
Controller’s operational register space. When directly accessed in a memory cycle, reads
and writes of this register have no side effects.
Table 90.
HceControl register: bit description
Bit
Symbol
Description
31 to 9
-
reserved
8
A20S
A20 State: This bit indicates the current state of gate A20 on the keyboard
controller. It is used to compare against value written to 60h when GA20S
(Gate A20 Sequence) is active.
7
IRQ12A
IRQ12 Active: This bit indicates that a positive transition on IRQ12 from
the keyboard controller has occurred. Writing logic 1 sets IRQ12 to logic 0
(inactive). Writing logic 0 to this bit has no effect.
6
IRQ1A
IRQ1 Active: This bit indicates that a positive transition on IRQ1 from the
keyboard controller has occurred. Writing logic 1 sets IRQ1 to logic 0
(inactive). Writing logic 0 to this bit has no effect.
5
GA20S
Gate A20 Sequence: This bit is set by the Host Controller when a data
value of D1h is written to I/O port 64h and cleared, on a write to I/O port
64h of any value other than D1h.
4
EIRQEN
External IRQ Enable: When this bit is set to logic 1, IRQ1 and IRQ12 from
the keyboard controller cause an emulation interrupt. This bit is
independent of the setting of the EE (Emulation Enable) bit in this register.
3
IRQEN
IRQ Enable: When this bit is set, the Host Controller generates IRQ1 or
IRQ12 as long as the OUT_FULL (Output Full) bit in HceStatus is set to
logic 1. If the AUX_OUT_FULL (Auxiliary Output Full) bit of HceStatus is
logic 0, then IRQ1 is generated; if it is logic 1, then an IRQ12 is generated.
2
C_P
Character Pending: When this bit is set, an emulation interrupt is
generated when the OUT_FULL (Output Full) bit of the HceStatus register
is set to logic 0.
1EI
Emulation Interrupt: This bit shows the emulation interrupt condition.
0 — Legacy emulation enabled
1 — Legacy emulation disabled
0EE
Emulation Enable: When this bit is set to logic 1, the Host Controller is
enabled for legacy emulation. The Host Controller decodes accesses to
I/O registers 60h and 64h, and enables interrupts on IRQ1 or IRQ12, or
both. The Host Controller also generates an emulation interrupt at
appropriate times to invoke the emulation software.
Table 91.
HceInput register: bit allocation
Bit
31
30
29
28
27
26
25
24
Symbol
reserved
Reset
00000000
Access
--------
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