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参数资料
型号： ISP1561BM,557
厂商： ST-ERICSSON
元件分类： 总线控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封装： 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-128
文件页数： 48/103页
文件大小： 457K
代理商： ISP1561BM,557
ISP1561_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 5 March 2007
49 of 103
NXP Semiconductors
ISP1561
HS USB PCI Host Controller
11.1.13 HcDoneHead register (address: content of the base address register + 30h)
The HcDoneHead register contains the physical address of the last completed TD that
was added to the done queue. In a normal operation, the HCD need not read this register
because its content is periodically written to the HCCA. Table 67 contains the bit allocation
of the register.
Table 66.
HcBulkCurrentED register: bit description
Bit
Symbol
Description
31 to 4
BCED[27:0]
Bulk Current ED: This is advanced to the next ED after the Host
Controller has served the present ED. The Host Controller continues
processing the list from where it left off in the last frame. When it reaches
the end of the bulk list, the Host Controller checks the CLF (Control List
Filled) bit of HcControl. If the CLF bit is not set, nothing is done. If the CLF
bit is set, it copies the content of HcBulkHeadED to HcBulkCurrentED and
clears the CLF bit. The HCD can only modify this register when the BLE
(Bulk List Enable) bit of HcControl is cleared. When HcControl is set, the
HCD reads the instantaneous value of this register. This is initially set to
logic 0 to indicate the end of the bulk list.
3 to 0
-
reserved
Table 67.
HcDoneHead register: bit allocation
Bit
31
30
29
28
27
26
25
24
Symbol
DH[27:20]
Reset
00000000
Access
R/W
Bit
23
22
21
20
19
18
17
16
Symbol
DH[19:12]
Reset
00000000
Access
R/W
Bit
15
14
13
12
11
10
9
8
Symbol
DH[11:4]
Reset
00000000
Access
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
DH[3:0]
reserved
Reset
00000000
Access
R/W
----
Table 68.
HcDoneHead register: bit description
Bit
Symbol
Description
31 to 4
DH[27:0]
Done Head: When a TD is completed, the Host Controller writes the
content of HcDoneHead to the NextTD eld of the TD. The Host
Controller then overwrites the content of HcDoneHead with the
address of this TD. This is set to logic 0 whenever the Host Controller
writes the content of this register to HCCA.
3 to 0
-
reserved
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