参数资料
型号: ISP1561BM,557
厂商: ST-ERICSSON
元件分类: 总线控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封装: 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-128
文件页数: 80/103页
文件大小: 457K
代理商: ISP1561BM,557
ISP1561_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 5 March 2007
78 of 103
NXP Semiconductors
ISP1561
HS USB PCI Host Controller
11.4.8 CONFIGFLAG register (address: content of the base address register + 4Ch)
The bit allocation of the Congure Flag (CONFIGFLAG) register is given in Table 116.
Bit
15
14
13
12
11
10
9
8
Symbol
LPL[10:3]
Reset
00000000
Access
R/W
----
Bit
7
6
5
4
3
2
1
0
Symbol
LPL[2:0]
reserved
Reset
00000000
Access
--------
Table 115. ASYNCLISTADDR register: bit description
Bit
Symbol
Description
31 to 5
LPL[26:0] Link Pointer List: These bits correspond to memory address signals 31 to
5, respectively. This eld may only reference a Queue Head (QH).
4 to 0
-
reserved
Table 116. CONFIGFLAG register: bit allocation
Bit
31
30
29
28
27
26
25
24
Symbol
reserved
Reset
00000000
Access
--------
Bit
23
22
21
20
19
18
17
16
Symbol
reserved
Reset
00000000
Access
--------
Bit
15
14
13
12
11
10
9
8
Symbol
reserved
Reset
00000000
Access
--------
Bit
7
6
5
4
3
2
1
0
Symbol
reserved
CF
Reset
00000000
Access
-------
R/W
Table 117. CONFIGFLAG register: bit description
Bit
Symbol
Description
31 to 1
-
reserved
0CF
Congure Flag: The host software sets this bit as the last action in its
process of conguring the Host Controller. This bit controls the default
port-routing control logic.
0 — Port routing control logic default-routes each port to an implementation
dependent classic Host Controller
1 — Port routing control logic default-routes all ports to this Host Controller
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