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参数资料
型号： ISP1561BM,557
厂商： ST-ERICSSON
元件分类： 总线控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封装： 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-128
文件页数： 50/103页
文件大小： 457K
代理商： ISP1561BM,557
ISP1561_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 5 March 2007
50 of 103
NXP Semiconductors
ISP1561
HS USB PCI Host Controller
11.1.14 HcFmInterval register (address: content of the base address register + 34h)
The HcFmInterval register contains a 14-bit value that indicates the bit time interval in a
frame, that is, between two consecutive SOFs, and a 15-bit value indicating the full-speed
maximum packet size that the Host Controller may transmit or receive, without causing a
scheduling overrun. The HCD may carry out minor adjustment on the FI (Frame Interval)
by writing a new value over the present at each SOF. This provides the possibility for the
Host Controller to synchronize with an external clocking resource and to adjust any
unknown local clock offset. The bit allocation of the register is given in Table 69.
Table 69.
HcFmInterval register: bit allocation
Bit
31
30
29
28
27
26
25
24
Symbol
FIT
FSMPS[14:8]
Reset
00000000
Access
R/W
Bit
23
22
21
20
19
18
17
16
Symbol
FSMPS[7:0]
Reset
00000000
Access
R/W
Bit
15
14
13
12
11
10
9
8
Symbol
reserved
FI[13:8]
Reset
00101110
Access
-
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
FI[7:0]
Reset
11011111
Access
R/W
Table 70.
HcFmInterval register: bit description
Bit
Symbol
Description
31
FIT
Frame Interval Toggle: The HCD toggles this bit whenever it loads
a new value to Frame Interval.
30 to 16
FSMPS[14:0]
FS Largest Data Packet: This eld species a value that is loaded
into the largest data packet counter at the beginning of each frame.
The counter value represents the largest amount of data in bits that
can be sent or received by the Host Controller in a single
transaction at any given time, without causing a scheduling
overrun. The eld value is calculated by the HCD.
15 to 14
-
reserved
13 to 0
FI[13:0]
Frame Interval: This species the interval between two
consecutive SOFs in bit times. The nominal value is set to 11,999.
The HCD must store the current value of this eld before resetting
the Host Controller because this causes the eld to be reset the
nominal value. The HCD can then restore the stored value on
completing the reset sequence.
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