参数资料
型号: ISP1561BM,557
厂商: ST-ERICSSON
元件分类: 总线控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封装: 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-128
文件页数: 42/103页
文件大小: 457K
代理商: ISP1561BM,557
ISP1561_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 5 March 2007
43 of 103
NXP Semiconductors
ISP1561
HS USB PCI Host Controller
11.1.6 HcInterruptDisable register (address: content of the base address register +
14h)
Each disable bit in the HcInterruptDisable register corresponds to an associated interrupt
bit in the HcInterruptStatus register. The HcInterruptDisable register is coupled with the
HcInterruptEnable register. Therefore, writing logic 1 to a bit in this register clears the
corresponding bit in the HcInterruptEnable register, whereas writing logic 0 to a bit in this
register leaves the corresponding bit in the HcInterruptEnable register unchanged. On a
read, the current value of the HcInterruptEnable register is returned. The register contains
4 bytes, and the bit allocation is given in Table 53.
3RD
Resume Detect:
0 — Ignore
1 — Enables interrupt generation because of resume detect
2SF
Start-of-Frame:
0 — Ignore
1 — Enables interrupt generation because of Start-of-Frame
1
WDH
HcDoneHead Write-back:
0 — Ignore
1 — Enables interrupt generation because of HcDoneHead write-back
0SO
Scheduling Overrun:
0 — Ignore
1 — Enables interrupt generation because of scheduling overrun
Table 52.
HcInterruptEnable register: bit description …continued
Bit
Symbol
Description
Table 53.
HcInterruptDisable register: bit allocation
Bit
31
30
29
28
27
26
25
24
Symbol
MIE
OC
reserved
Reset
00000000
Access
R/W
------
Bit
23
22
21
20
19
18
17
16
Symbol
reserved
Reset
00000000
Access
--------
Bit
15
14
13
12
11
10
9
8
Symbol
reserved
Reset
00000000
Access
--------
Bit
7
6
5
4
3
2
1
0
Symbol
reserved
RHSC
FNO
UE
RD
SF
WDH
SO
Reset
00000000
Access
-
R/W
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