register
26 Wed May 28 17:37:25 1997
Draft 1/21/97
4-26
Registers
PRE.4 for Rev. D
Copyright 1997 by LSI Logic Corporation. All rights reserved.
SYNC_DEL
Synchronization Delay Select
4
This bit species the number of synchronization registers
used to synchronize AREQ and VREQ. If this bit is set to
0, AREQ and VREQ are synchronized by one register; if
set to 1, AREQ and VREQ are synchronized by two reg-
isters. The A/V output is delayed by one cycle if this bit
is set to 0; it is delayed by two cycles if this bit is set to 1.
This bit solves the metastable problem of using two sep-
arate devices with different clocking schemes. When
using the L64002 with the same clock as the L64007, this
bit should be set to 0.
AV_DEL
Cycle Delay
[3:2]
This 2-bit eld sets the minimum recovery time after the
rising edges of AV_CS, AVALID, and VVALID in parallel
output mode. This reduces the output bit rate to the
L64002. For example, if set to 2, it reduces the rate to
one third of the AV_RATE. When using the L64002, this
bit should be set to 2 delay cycles.
AV_RATE
Audio/Video Output Channel Rate
[1:0]
This 2-bit eld sets the data transfer rate for serial or par-
allel mode.
AV_RATIO
Bits/Bytes of Video per 1 bit/byte of Audio
000000
no output
000001
1 bit/byte audio per 1 bit/byte video
000010
1 bit/byte audio per 2 bit/byte video
000011
1 bit/byte audio per 3 bit/byte video
.
111111
1 bit/byte audio per 64 bit/byte video
Bit Setting
Delay (cycles)
Output Rate
00
Not allowed.
Not allowed
01
1
One half
10
2 (minimum require-
ment of L64002)
One third
11
3
One fourth