
register
14 Wed May 28 17:37:25 1997
Draft 1/21/97
4-14
Registers
PRE.4 for Rev. D
Copyright 1997 by LSI Logic Corporation. All rights reserved.
Status Queue. When reset to 0, this PID does not gener-
ate an interrupt, and no status word is saved in the PID
Status Queue.
ACT
Active
13
When set to 1, the PPU lters the stream for this PID;
otherwise, it does not.
0
Zero
[12:11]
These bits are zero.
1
One
10
This bit must be set to 1.
AF
Post AF
9
When set to 1, this bit indicates that the adaptation eld
in this PID is posted to the MMU. When set to 0, the
adaptation eld is not posted.
AUX
Post to AUX Port
8
When set to 1, the transport packet of this PID is posted
to the AUX port. This is done in parallel to the payload
data and adaptation eld of this packet, which are posted
to the external DRAM or host interface according to the
DES control bit. When set to 0, the transport packet of
this PID is not posted to the AUX port.
RES
Reserved
[7:0]
These bits are reserved.
4.4.3
Video Splice
PID Value
(VSPV)
The VSPV is a 13-bit read/write register representing the ID of the video
PID to switch to during a splice operation. The VPID Register bit eld is
described below.
VSPV
Video Splice PID Value
[12:0]
This 13-bit eld determines the value to be compared
with the PID eld transmitted in the transport packet
header. If the PID value matches the VSPV, and the ACT
bit in the VUCR is set to 1, the PPU continues to parse
the data in this transport packet. The payload in this
15
13
12
0
RES
VSPV