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参数资料
| 型号： | M-ORT82G52BM680-DB |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封装： | PLASTIC, FBGA-680 |
| 文件页数： | 12/94页 |
| 文件大小： | 2104K |
| 代理商： | M-ORT82G52BM680-DB |
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Lattice Semiconductor
ORCA ORT82G5 Data Sheet
2
High-speed SERDES with programmable serial data rates including 1.0 Gbits/s, 1.25 Gbits/s, 2.5 Gbits/s, 3.125
Gbits/s, and 3.7 Gbits/s. Operation has been demonstrated on design tolerance devices at 3.7 Gbits/s across 26
in. of FR-4 backplane and at 3.2 Gbits/s across 40 in. of FR-4 backplane across temperature and voltage speci-
cations.
Asynchronous operation per receive channel with the receiver frequency tolerance based on one reference clock
per quad channels (separate PLL per channel).
Ability to select full-rate or half-rate operation per transmit or receive channel by setting the appropriate control
registers.
Programmable one-half amplitude transmit mode for reduced power in chip-to-chip application.
Transmit preemphasis (programmable) for improved receive data eye opening.
32-bit (8b/10b) or 40-bit (raw data) parallel internal bus for data processing in FPGA logic.
Provides a 10 Gbits/s backplane interface to switch fabric. Also supports port cards at 40 Gbits/s or 2.5 Gbits/s.
3.125 Gbits/s SERDES compliant with XAUI serial data specication for 10 G Ethernet applications with protec-
tion.
Most XAUI features for 10 G Ethernet are embedded including the required link state machine.
Compliant to Fibre Channel physical layer specication.
High-Speed Interface (HSI) function for clock/data recovery serial backplane data transfer without external
clocks.
Eight-channel HSI function provides 2.96 Gbits/s serial user data interface per channel for a total chip bandwidth
of 23.68 Gbits/s (full duplex).
SERDES has low-power CML buffers. Support for 1.5 V/1.8 V I/Os. Allows use with optical transceiver, coaxial
copper media, shielded twisted pair wiring or high-speed backplanes such as FR-4.
Power down option of SERDES HSI receiver or transmitter on a per-channel basis.
Automatic lock to reference clock in the absence of valid receive data.
Per channel Pseudo-Random Bit Sequence (PRBS) generator and checker.
High-speed and low-speed loopback test modes.
Requires no external component for clock recovery and frequency synthesis.
SERDES characterization pins available to control/monitor the internal interface to one SERDES quad macro.
SERDES HSI automatically recovers from loss-of-clock once its reference clock returns to normal operating
state.
Built-in boundary scan (IEEE
1149.1 and 1149.2 JTAG) for the programmable I/Os, not including the SERDES
interface.
FIFOs can align incoming data either across all eight channels (all eight channels, across two groups of four
channels, or across four groups of two channels). Alignment is done either using comma characters or by using
the /A/ character in XAUI mode. Optionally, the alignment FIFOs can be bypassed for asynchronous operation
between channels. (Each channel includes its own clock and frame pulse or comma detect.)
Addition of two 4K X 36 dual-port RAMs with access to the programmable logic.
Pinout compatible to the ORCA ORSO82G5 SONET backplane driver FPSC.
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