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参数资料
| 型号： | M-ORT82G52BM680-DB |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封装： | PLASTIC, FBGA-680 |
| 文件页数： | 37/94页 |
| 文件大小： | 2104K |
| 代理商： | M-ORT82G52BM680-DB |
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Lattice Semiconductor
ORCA ORT82G5 Data Sheet
42
Figure 23. Pseudo-Random Bit Sequence (PRBS) Generate and Check Logic
The receiver rst deserializes the incoming serial data to regenerate the transmitted 10-bit word. The PRBS
checker on the receiver compares the regenerated 10-bit word to an internally calculated 10-bit word on a word by
word basis and signals a mismatch by asserting a PRBSCHK alarm status bit.
The PRBS checker also contains a watchdog timer which asserts the time-out alarm status bit, PRBSTOUT_xx, if
the PRBS test cannot progress beyond its start state within a reasonable time interval. Both the PRBSCHK_xx and
the PRBSTOUT_xx alarms can generate an interrupt if their corresponding masks are disabled (MPRBSCHK_xx =
MPRBSTOUT_xx = 0).
Loopback Testing
Loopback testing is performed by looping back (either internal to the Embedded Core, by conguring the FPGA
logic or by external connections) transmitted data to the corresponding receiver inputs, or received data to the
transmitter output. The loopback path may be either serial or parallel.
In general, loopback tests can be classied as “near end” or “far end.” In “near end” loopback (Figure 24(a)), data is
generated and checked locally, i.e. by logic on, or connection of, test equipment to the same card as the FPSC. In
“far end” loopback (Figure 24(b)), the generating and checking functions are performed remotely, either by test
equipment or a remote system card.
PRBS
Checker
CML
Buffer
1:10
DEMUX
8B/10B
Decode
To Status Register
PRBSCHK
PRBSTOUT
Receive
HDIN[P:N]_xx
2
HDOUT[P:N]_xx
2
CML
Buffer
10:1
MUX
8B/10B
Encode
PRBS
Generator
Transmit
MUX
10
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