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参数资料
| 型号： | M-ORT82G52BM680-DB |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封装： | PLASTIC, FBGA-680 |
| 文件页数： | 48/94页 |
| 文件大小： | 2104K |
| 代理商： | M-ORT82G52BM680-DB |
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Lattice Semiconductor
ORCA ORT82G5 Data Sheet
52
SERDES Common Transmit and Receive Channel Conguration Registers (Read/Write), xx=[AA, ...,BD]
30004 - AA
30014 - AB
30024 - AC
30034 - AD
30104 - BA
30114 - BB
30124 - BC
30134 - BD
[0]
PRBS_xx
40
Transmit and Receive PRBS Enable Bit, Channel xx. When PRBS_xx =
1, both the transmitter's PRBS generator and the receiver's PRBS
checker are enabled. GRBS_[A:B] overrides these bits if set.
NOTE: Due to timing, PRBS mode is intended for use with internally or
externally looped-back data only.
PRBS_xx = 0 on device reset.
[1]
MASK_xx
Transmit and Receive Alarm Mask Bit, Channel xx. When MASK_xx = 1,
the transmit and receive alarms of a channel are prevented from gener-
ating an interrupt (i.e., they are masked or disabled). The MASK_xx bit
overrides the individual alarm mask bits in the Alarm Mask Registers.
MASK_xx = 1 on device reset.
[2]
SWRST_xx
Transmit and Receive Software Reset Bit, Channel xx. When
SWRST_ss = 1, this bit provides the same function as the hardware
reset, except that all conguration register settings are unaltered. This is
not a self-clearing bit. Once set, this bit must be manually set and
cleared.
SWRST = 0 on device reset.
[3:6]
Not Used
[7]
TESTEN_xx
Transmit and Receive Test Enable Bit, Channel xx. When TESTEN_xx =
1, the transmit and receive sections are placed in test mode. The
TestMode_[A:B][4:0] bits in the Global Control Registers specify the par-
ticular test, and must also be set.
NOTE: When the global test enable bit GTESTEN_[A:B] = 0, the individ-
ual channel test enable bits are used to selectively place a channel in
test or normal mode. When GTESTEN_[A:B] = 1, all channels are set to
test mode regardless of their TESTEN setting
TESTEN_xx = 0 on device reset.
Table 20. Memory Map (Continued)
(0x)
Absolute
Address
Bit
Name
Reset
Value
(0x)
Description
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