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参数资料
| 型号： | M-ORT82G52BM680-DB |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封装： | PLASTIC, FBGA-680 |
| 文件页数： | 32/94页 |
| 文件大小： | 2104K |
| 代理商： | M-ORT82G52BM680-DB |
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Lattice Semiconductor
ORCA ORT82G5 Data Sheet
38
The receive channel alignment bypass mode allows mixing of half and full line rates among the channels, as shown
in Figure 19. The gure shows channel pair AA and AB congured in full rate mode at 2.0 Gbits/s. Channel pair AC
and AD are congured in half-rate mode at 1.0 Gbits/s.
Figure 19. Receive Clocking for Mixed Line Rates
As noted in the caption of Figure 19, each quad can be congured in any line rate (1.0-3.7 Gbits/s), since each
quad has its own reference clock input pins. The receive alignment FIFO per channel cannot be used in this mode.
Multi-Channel Alignment Clocking Strategies
The data on the 8 channels (4 per SERDES quad) in the ORT82G5 can be independent of each other or can be
synchronized in several ways. For example, two channels within a SERDES can be aligned together; channel A
and B and/or channel C and D. Alternatively, all four channels in a SERDES quad can be aligned together to form a
communication channel with a bandwidth of 10 Gbits/s. Finally, the alignment can be extended across both SER-
DES quads to align all 8 channels. Individual channels within an alignment group can be disabled (i.e., powered
down) without disrupting other channels. Clocking strategies for these various modes are described in the following
paragraphs.
For dual alignment both twins within a quad can be sourced by clocks that are different from the other channels,
however each pair of SERDES must have the same clock. The channel pair AA and AB is driven on the low speed
side by RSYS_CLK_A1 and the channel pair AC and AD are driven on the low speed side by RSYS_CLK_A2.
Either RWCKAA or RWCKAB can be connected to RSYS_CLK_A1 and either RWCKAC or RWCKAD can be con-
nected to RSYS_CLK_A2. A clocking example for dual alignment is shown in Figure 20.
Common Logic, Quad A
Channel AA
Channel AB
Channel AD
Channel AC
REFCLK[P:N]_A
2
100 MHz
RCK78A
RWCKAA
RWCKAC
RSYS_CLK_A1
TSYS_CLK_AD
FPGA
Logic
Two Channels of
2.0 Gbits/s (Full-Rate)
Incoming Serial Data
25 MHz
RWCKAB
RWCKAD
Recovered
Clocks at
25 MHZ
or 50 MHz
{
Recovered
Clocks at
50 MHZ
{
Two Channels of
1.0 Gbits/s (Half-Rate)
Incoming Serial Data
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