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参数资料
| 型号： | M-ORT82G52BM680-DB |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封装： | PLASTIC, FBGA-680 |
| 文件页数： | 19/94页 |
| 文件大小： | 2104K |
| 代理商： | M-ORT82G52BM680-DB |
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Lattice Semiconductor
ORCA ORT82G5 Data Sheet
26
Each channel is provided with a 24 word x 36-bit FIFO. The FIFO can perform two tasks: (1) to change the clock
domain from receive clock to a clock from the FPGA side, and (2) to align the receive data over 2, 4, or 8 channels.
This FIFO allows a timing budget of ±230.4 ns that can be allocated to skew between the data lanes and for trans-
fer to the system clock. The input to the FIFO consists of 36 bits of demultiplexed data, RALIGN_xx[3:0],
RWD_xx[31:0], and RWBIT8_xx[3:0].
The four RALIGN_xx bits are control signals, and can be the alignment character detect signals indicating the pres-
ence of a comma character in Fibre Channel mode and the /A/ character in XAUI mode. The other 32 RWD_xx bits
are the 8-bit data bytes from the 8b/10b decoder. The alignment character, if present, is the MSB of the data. The
RWBIT8_xx indicates the presence of a Km.n control character in the receive data byte. Only RWBIT8_xx and
RWD_xx inputs are stored in the FIFO. During alignment process, RALIGN[3]_xx is used to synchronize multiple
channels.
If a channel is not in any alignment group, it will set the FIFO-write-address to the beginning of the FIFO, and will
set the FIFO-read-address to the middle of the FIFO, at the rst assertion of RALIGN[3]_xx after reset or after the
resync command.
The RX_FIFO_MIN_xx register bits can be used to control the threshold for minimum unused buffer space in the
alignment FIFOs between read and write pointers before overow (OVFL) status is agged. The synchronization
algorithm consists of a down counter which starts to count down by 1 from its initial value of 18 (decimal) when an
alignment character from any channel within an alignment group has been received. Once all the alignment char-
acters within the alignment group have been received, the count is decremented by 2 until 0 is reached. Data is
then read from the FIFOs and output to the FPGA. This algorithm is not repeated after multi-channel alignment has
been achieved; resynchronization must be forced by toggling the appropriate FMPU_RESYNC bit.
The ORT82G5 has a total of 8 channels (4 per SERDES). The incoming data of these channels can be synchro-
nized in several ways or they can be independent of one other. Two channels within a SERDES quad can be
aligned together. Channel A and B and/or channel C and D can form a pair as shown in Figure 11. Alternately, all
four channels of a SERDES quad can be aligned together to form a communication channel with a bandwidth of 10
Gbits/s as shown in Figure 12. Finally, the alignment can be extended across both SERDES quad to align all 8
channels in ORT82G5 as shown in Figure 13. Individual channels within an alignment group can be disabled (i.e.,
powered down) without disrupting other channels.
Figure 11. Twin Channel Alignment
Channel AB
Channel AC
Channel AD
Channel BA
Channel BB
Channel BC
Channel BD
Channel AA
Channel AB
Channel AC
Channel AD
Channel BA
Channel BB
Channel BC
Channel BD
t2
Channel AA
t1
t0
t3
TWIN ALIGNMENT OF CHANNELS AA AND AB
TWIN ALIGNMENT OF CHANNELS AC AND AD
TWIN ALIGNMENT OF CHANNELS BA AND BB
TWIN ALIGNMENT OF CHANNELS BC AND BD
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