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参数资料
| 型号： | M-ORT82G52BM680-DB |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封装： | PLASTIC, FBGA-680 |
| 文件页数： | 89/94页 |
| 文件大小： | 2104K |
| 代理商： | M-ORT82G52BM680-DB |
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Lattice Semiconductor
ORCA ORT82G5 Data Sheet
9
Additional Information
Contact your local Lattice representative for additional information regarding the ORCA Series 4 FPGA devices, or
visit the Lattice web site at www.latticesemi.com..
ORT82G5 Overview
The ORT82G5 FPSC provides high-speed backplane transceivers combined with FPGA logic. It is based on 1.5 V
OR4E04 ORCA FPGA and has a 36 x 36 array of Programmable Logic Cells (PLCs). The embedded core, which
contains the backplane transceivers is attached to the right side of the device and is integrated directly into the
FPGA array. A top level diagram of the basic chip conguration is shown in Figure 1.
Embedded Core Overview
The embedded core portion of the ORT82G5 contains eight Clock and Data Recovery (CDR) macrocells and eight
Serialize/Deserialize (SERDES) blocks and supports eight channels of 8b/10b (IEEE 802.3z) encoded serial links.
It is intended for high-speed serial backplane data transmission. Figure 1 shows the ORT82G5 top level block dia-
gram and the basic data ow. Boundary scan for the ORT82G5 only includes programmable I/Os and does not
include any of the embedded block I/Os.
Figure 1. ORT82G5 Top Level Block Diagram
The ORT82G5’s eight channels can each operate at up to 3.7 Gbits/s (2.96 Gbits/s data rate) with a full-duplex
synchronous interface with built-in clock recovery (CDR). The 8b/10b encoding provides guaranteed ones density
for the CDR, byte alignment, and error detection. The core is also capable of frame synchronization and physical
link monitoring and contains independent 4k x 36 RAM blocks. Overviews of the various blocks in the embedded
core are presented in the following paragraphs.
Serializer and Deserializer (SERDES)
The SERDES portion of the core contains two quad transceiver blocks for serial data transmission at a selectable
data rate of 1.0-3.7 Gbits/s.Each SERDES channel features high-speed 8b/10b parallel I/O interfaces to other core
blocks and high-speed CML interfaces to the serial links.
The SERDES circuitry consists of receiver, transmitter, and auxiliary functional blocks. The receiver accepts high-
speed (up to 3.7 Gbits/s) serial data. Based on data transitions, the receiver locks an analog receive PLL for each
channel to retime the data, then demultiplexes the data down to parallel bytes and an accompanying clock.
The transmitter operates in the reverse direction. Parallel bytes are multiplexed up to 3.7 Gbits/s serial data for off-
chip communication. The transmitter generates the necessary 3.7 GHz clocks for operation from a lower speed ref-
erence clock
SERDES w/
CLOCK/DATA
BYTE-
WIDE
DATA
8b/10b
DECODER/ENCODER
8 FULL-
1.0 Gbits/s
DATA
DUPLEX
SERIAL
CHANNELS
TO
3.7 Gbits/s
1.0 Gbits/s
DATA
TO
3.7 Gbits/s
CML
I/Os
ORCA
SERIES 4
FPGA LOGIC
STANDARD
FPGA I/Os
4:1 MUX/1:4 DEMUX
RECOVERY
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