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| 型号： | M-ORT82G52BM680-DB |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封装： | PLASTIC, FBGA-680 |
| 文件页数： | 3/94页 |
| 文件大小： | 2104K |
| 代理商： | M-ORT82G52BM680-DB |
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Lattice Semiconductor
ORCA ORT82G5 Data Sheet
11
FPSC Conguration
Conguration of the ORT82G5 occurs in two stages: FPGA bitstream conguration and embedded core setup.
Prior to becoming operational, the FPGA goes through a sequence of states, including power up, initialization, con-
guration, start-up, and operation. The FPGA logic is congured by standard FPGA bit stream conguration means
as discussed in the Series 4 FPGA data sheet.
After the FPGA conguration is complete, the options for the embedded core are set based on the contents of reg-
isters that are accessed through the FPGA system bus.
The system bus itself can be driven by an external PowerPC compliant microprocessor via the MPI block or via a
user master interface in FPGA logic. A simple IP block that drives the system by using the user register interface
and very little FPGA logic is available in the MPI/System Bus Technical Note. This IP block sets up the embedded
core via a state machine and allows the ORT82G5 to work in an independent system without an external micropro-
cessor interface.
Backplane Transceiver Core Detailed Description
The following sections describe the various logic blocks in the Embedded Core portion of the FPSC. The FPGA
section of the FPSC is identical to an ORCA 4E4 FPGA except that the pads on one edge of the FPGA chip are
replaced by the Embedded Core. For a detailed description of the programmable logic functions, please see the
ORCA Series 4 Data Sheet and related application and technical notes.
The major functional blocks in the Embedded Core include:
Two quad-channel SERializer-DESerializer (SERDES) blocks
8b/10b encoder/decoders
4-to-1 multiplexers (MUX) and 1-to-4 demultiplexers (DEMUX)
Fibre channel synchronization state machine
XAUI link alignment state machine
Alignment FIFOs
Embedded 4K x 36 RAM blocks (independent from transceiver logic).
A top level block diagram of the Embedded Core Logic is shown in Figure 2. The Embedded RAM blocks are not
shown. The external pins for the Embedded Core are listed later in this data sheet in and the signals at the Embed-
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