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参数资料
| 型号： | M-ORT82G52BM680-DB |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封装： | PLASTIC, FBGA-680 |
| 文件页数： | 28/94页 |
| 文件大小： | 2104K |
| 代理商： | M-ORT82G52BM680-DB |
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Lattice Semiconductor
ORCA ORT82G5 Data Sheet
34
the data rate and bit-width so the FPGA core can run at 1/4th this frequency which gives a range of 25 to 92.5 MHz
for the data in and out of the FPGA.
Internal Clock Signals at the FPGA/Core Interface
There are several clock signals dened at the FPGA/Embedded Core interface in addition to the external reference
clock for each SERDES quad. All of the ORT82G5 clock signals are shown in Figure 15 and are described follow-
ing the gure.
Figure 15. ORT82G5 Clock Signals (High Speed Serial I/O Also Shown)
REFCLKP_[A:B], REFCLKN_[A:B]:
These are the differential reference clocks provided to the ORT82G5 device as described earlier. They are used as
the reference clock for both TX and RX paths. For operation of the serial links at 3.125 Gbits/s, the reference clocks
will be at a frequency of 156.25 MHz.
RWCK[AA:BD]:
These are the low-speed receive clocks from the embedded core to the FPGA across the core-FPGA interface.
These are derived from the recovered low-speed complementary clocks from the SERDES blocks. RWCK_AA
belongs to Channel AA, RWCK_AB belongs to channel AB and so on. With a reference clock input of 156.25 MHz,
these clocks operate at 78.125 MHz.
RCK78[A:B]:
These are muxed outputs of RWCKA[A:D] and RWCKB[B:D] respectively. With a reference clock input of 156.25
MHz, these clocks operate at 78.125 MHz.
FPGA
Logic
Common Logic, Quad A
Channel AA
Channel AB
Channel AD
Channel AC
Common Logic, Quad B
Channel BA
Channel BB
Channel BD
Channel BC
RCK78A
TCK78A
RSYS_CLK_A1
TSYS_CLK_AA
RWCKAA
RWCKAB
TSYS_CLK_AB
RWCKAC
TSYS_CLK_AC
RSYS_CLK_A2
TSYS_CLK_AD
RWCKAD
RCK78B
TCK78B
RSYS_CLK_B1
TSYS_CLK_BA
RWCKBA
RWCKBB
TSYS_CLK_BB
RSYS_CLK_B2
RWCKBD
RWCKBC
TSYS_CLK_BC
TSYS_CLK_BD
REFCLK[P:N]_A
2
HDIN[P:N]_AC
2
HDOUT[P:N]_AD
HDIN[P:N]_AD
2
HDOUT[P:N]_AC
HDOUT[P:N]_AB
2
HDIN[P:N]_AB
2
HDOUT[P:N]_AA
2
HDIN[P:N]_AA
2
REFCLK[P:N]_B
HDIN[P:N]_BC
2
HDIN[P:N]_BD
2
HDIN[P:N]_BB
2
HDIN[P:N]_BA
2
HDOUT[P:N]_BA
HDOUT[P:N]_BB
HDOUT[P:N]_BC
HDOUT[P:N]_BD
2
TCK78A
Backplane
Serial
Link
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