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参数资料
| 型号： | M-ORT82G52BM680-DB |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封装： | PLASTIC, FBGA-680 |
| 文件页数： | 9/94页 |
| 文件大小： | 2104K |
| 代理商： | M-ORT82G52BM680-DB |
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Lattice Semiconductor
ORCA ORT82G5 Data Sheet
17
Since this effect is predictable for a given type of PCB material, it is possible to compensate for this effect in two
ways - transmitter preemphasis and receiver equalization. Each of these techniques boosts the high frequency
components of the signal but transmit preemphasis is preferred due to the ease of implementation and the better
power utilization. It also gives a better signal-to-noise ratio because receiver equalization amplies both the signal
and the noise at the receiver
Applying too much preemphasis when it is not required, for example when driving a short backplane path, will also
degrade the data eye opening at the receiver. In the ORT82G5 the degree of transmit preemphasis can be pro-
grammed with a two-bit control from the microprocessor interface as shown in Table 3. The high-pass transfer func-
tion of the preemphasis circuit is given by the following equation, where the value of a is shown in Table 3.
H(z) = (1 – az
–1)
(1)
Table 3. Preemphasis Settings
Receive Path (Backplane → FPGA) Logic
The receiver section receives high-speed serial data at the external differential CML input pins. These data are fed
to the clock recovery section which generates a recovered clock and retimes the data. Therefore the receive clocks
are asynchronous between channels. The retimed data are deserialized and presented as a 10-bit encoded or a 8-
bit unencoded parallel data on the output port. The receiver also optionally recognizes comma characters, detects
code violations and aligns the bit stream to the proper word boundary.
As shown in Figure 6, the basic blocks in the receive path include:
Receive SERDES Block
CML input buffer
Receive PLL
1:10 demultiplexer (DEMUX)
Clock and Data Recovery (CDR) section
PRBS checker
10B/8B decoder
1:4 demultiplexer and Embedded Core/FPGA interface
1:4 DEMUX
Low speed parallel Embedded Core/FPGA logic interface
Multi-channel alignment logic
PE1
PE0
Amount of Preemphasis (a)
0
0% (No Preemphasis)
0
1
12.5%
1
0
12.5%
1
25%
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