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参数资料
| 型号： | M-ORT82G52BM680-DB |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封装： | PLASTIC, FBGA-680 |
| 文件页数： | 49/94页 |
| 文件大小： | 2104K |
| 代理商： | M-ORT82G52BM680-DB |
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Lattice Semiconductor
ORCA ORT82G5 Data Sheet
53
SERDES Global Control Registers (ReadWrite) Acts on all four Channels in SERDES Quad A or SERDES Quad B.
30005 - A
30105 - B
[0]
GPRBS_[A:B]
44
Global PRBS Enable. The GPRBS_[A:B] bit globally enables the PRBS
generators and checkers of all four channels when GPRBS_[A:B] = 1.
GRBS_[A:B] overrides the PRBS_xx bits for the individual channels.
GPRBS_[A:B] = 0 on device reset.
[1]
GMASK_[A:B]
Global Mask. When GMASK_[A:B] = 1, the transmit and receive alarms
of all channel in the SERDES quad are prevented from generating an
interrupt (i.e., they are masked or disabled). The GMASK_[A:B] bit over-
rides the individual MASK_xx bits. GMASK_[A:B] = 1 on device reset.
[2]
GSWRST_[A:B]
Software reset bit. The GSWRST_[A:B] bit provides the same function
as the hardware reset for the transmit and receive sections of all four
channels, except that the device conguration settings are not affected
when GSWRST_[A:B] is asserted. This is not a self-clearing bit. Once
set, this bit must be manually set and cleared. The GSWRST_[A:B] bit
overrides the individual SWRST_xx bits. GSWRST_[A:B] = 0 on device
reset.
[3]
GPWRDNT_[A:B]
Powerdown Transmit Function. When GPWRDNT_[A:B] = 1, sections of
the transmit hardware for all four channels of are powered down to con-
serve power. The GPWRDNT_[A:B] bit overrides the individual
PWRDNT_xx bits.
GPWRDNT_[A:B] = 0 on device reset.
[4]
GPWRDNR_[A:B]
Powerdown Receive Function. When GPWRDNR_[A:B] = 1, sections of
the receive hardware for all four channels are powered down to conserve
power. The GPWRDNR_[A:B] bit overrides the individual PWRDNR_xx
bits.
GPWRDNR_[A:B] = 0 on device reset.
[5]
Reserved
Reserved, 1 on device reset.
[6]
Not Used
[7]
GTESTEN_[A:B]
Test Enable Control. When GTESTEN_[A:B] = 1, the transmit and
receive sections of all four channels are placed in test mode. The
GTESTEN_[A:B] bit overrides the individual TESTEN_xx bits.
GTESTEN_[A:B] = 0 on device reset.
30006 - A
30106 - B
[0:4]
TestMode[A:B]
00
TestMode - See Test Mode section for settings
[5]
Not Used
{6:7]
Reserved
Table 20. Memory Map (Continued)
(0x)
Absolute
Address
Bit
Name
Reset
Value
(0x)
Description
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